lectures.alex.balgavy.eu

Lecture notes from university.
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commit 2a17c7b5b29236d89eb3ca1473cdc9b330c0ac21
parent 52bef5718d92e540ab9f1ddc15467375329d7328
Author: Alex Balgavy <alex@balgavy.eu>
Date:   Mon, 24 Jan 2022 12:47:41 +0100

Add sysarch notes

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Mcontent/_index.md | 2+-
Dcontent/sysarch-notes/Accessing I_O devices.html | 4----
Acontent/sysarch-notes/Accessing I_O devices.md | 20++++++++++++++++++++
Dcontent/sysarch-notes/Adding_subtracting floating point values.html | 4----
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Acontent/sysarch-notes/Adding_subtracting floating point values/index.md | 12++++++++++++
Dcontent/sysarch-notes/Addition & subtraction with signed integers.html | 4----
Acontent/sysarch-notes/Addition & subtraction with signed integers/index.md | 17+++++++++++++++++
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Dcontent/sysarch-notes/Addition_subtraction logic unit.html | 4----
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Acontent/sysarch-notes/Addition_subtraction logic unit/index.md | 39+++++++++++++++++++++++++++++++++++++++
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Dcontent/sysarch-notes/Addressing modes.html | 4----
Acontent/sysarch-notes/Addressing modes/index.md | 23+++++++++++++++++++++++
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Dcontent/sysarch-notes/Assembly.html | 4----
Acontent/sysarch-notes/Assembly.md | 27+++++++++++++++++++++++++++
Dcontent/sysarch-notes/Basic concepts.html | 4----
Acontent/sysarch-notes/Basic concepts.md | 19+++++++++++++++++++
Dcontent/sysarch-notes/Basic logic gates.html | 4----
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Acontent/sysarch-notes/Basic logic gates/index.md | 46++++++++++++++++++++++++++++++++++++++++++++++
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Dcontent/sysarch-notes/Basic processing unit.html | 4----
Acontent/sysarch-notes/Basic processing unit.md | 61+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Dcontent/sysarch-notes/Branch delays.html | 4----
Acontent/sysarch-notes/Branch delays/index.md | 53+++++++++++++++++++++++++++++++++++++++++++++++++++++
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Dcontent/sysarch-notes/Buses.html | 4----
Acontent/sysarch-notes/Buses/index.md | 39+++++++++++++++++++++++++++++++++++++++
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Dcontent/sysarch-notes/Cache coherence.html | 4----
Acontent/sysarch-notes/Cache coherence.md | 61+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Dcontent/sysarch-notes/Cache memory.html | 4----
Acontent/sysarch-notes/Cache memory.md | 35+++++++++++++++++++++++++++++++++++
Dcontent/sysarch-notes/Conversion between bases.html | 4----
Acontent/sysarch-notes/Conversion between bases.md | 16++++++++++++++++
Dcontent/sysarch-notes/Counters.html | 4----
Acontent/sysarch-notes/Counters/index.md | 13+++++++++++++
Rcontent/sysarch-notes/Counters.resources/screenshot.png -> content/sysarch-notes/Counters/screenshot-3.png | 0
Dcontent/sysarch-notes/Data dependencies.html | 4----
Acontent/sysarch-notes/Data dependencies/index.md | 40++++++++++++++++++++++++++++++++++++++++
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Dcontent/sysarch-notes/Data path & instructions.html | 4----
Acontent/sysarch-notes/Data path & instructions/index.md | 50++++++++++++++++++++++++++++++++++++++++++++++++++
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Dcontent/sysarch-notes/Decoders.html | 4----
Acontent/sysarch-notes/Decoders/index.md | 9+++++++++
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Dcontent/sysarch-notes/Direct Memory Access (DMA).html | 4----
Acontent/sysarch-notes/Direct Memory Access (DMA).md | 15+++++++++++++++
Dcontent/sysarch-notes/Empirical Laws of Computing.html | 4----
Acontent/sysarch-notes/Empirical Laws of Computing.md | 11+++++++++++
Dcontent/sysarch-notes/Flip-Flops.html | 4----
Acontent/sysarch-notes/Flip-Flops/index.md | 45+++++++++++++++++++++++++++++++++++++++++++++
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Dcontent/sysarch-notes/Hardware components.html | 4----
Rcontent/sysarch-notes/Hardware components.resources/1200px-Von_Neumann_Architecture.svg.png -> content/sysarch-notes/Hardware components/1200px-Von_Neumann_Architecture.svg.png | 0
Rcontent/sysarch-notes/Hardware components.resources/CPU.png -> content/sysarch-notes/Hardware components/CPU.png | 0
Acontent/sysarch-notes/Hardware components/index.md | 43+++++++++++++++++++++++++++++++++++++++++++
Rcontent/sysarch-notes/Hardware components.resources/screenshot.png -> content/sysarch-notes/Hardware components/screenshot-59.png | 0
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Dcontent/sysarch-notes/Instruction Set Architecture.html | 4----
Acontent/sysarch-notes/Instruction Set Architecture.md | 29+++++++++++++++++++++++++++++
Dcontent/sysarch-notes/Instruction execution.html | 4----
Acontent/sysarch-notes/Instruction execution.md | 24++++++++++++++++++++++++
Dcontent/sysarch-notes/Internal organisation of memory chips.html | 4----
Acontent/sysarch-notes/Internal organisation of memory chips/index.md | 17+++++++++++++++++
Rcontent/sysarch-notes/Internal organisation of memory chips.resources/screenshot_1.png -> content/sysarch-notes/Internal organisation of memory chips/screenshot-36.png | 0
Rcontent/sysarch-notes/Internal organisation of memory chips.resources/screenshot.png -> content/sysarch-notes/Internal organisation of memory chips/screenshot-37.png | 0
Dcontent/sysarch-notes/Interrupts.html | 4----
Acontent/sysarch-notes/Interrupts/index.md | 48++++++++++++++++++++++++++++++++++++++++++++++++
Rcontent/sysarch-notes/Interrupts.resources/screenshot.png -> content/sysarch-notes/Interrupts/screenshot-32.png | 0
Dcontent/sysarch-notes/Karnaugh Maps.html | 4----
Acontent/sysarch-notes/Karnaugh Maps.md | 26++++++++++++++++++++++++++
Dcontent/sysarch-notes/Mapping functions.html | 4----
Acontent/sysarch-notes/Mapping functions.md | 40++++++++++++++++++++++++++++++++++++++++
Dcontent/sysarch-notes/Memory Hierarchy.html | 4----
Dcontent/sysarch-notes/Memory delays.html | 4----
Acontent/sysarch-notes/Memory delays/index.md | 22++++++++++++++++++++++
Rcontent/sysarch-notes/Memory delays.resources/screenshot.png -> content/sysarch-notes/Memory delays/screenshot-38.png | 0
Acontent/sysarch-notes/Memory hierarchy/index.md | 15+++++++++++++++
Rcontent/sysarch-notes/Memory Hierarchy.resources/screenshot.png -> content/sysarch-notes/Memory hierarchy/screenshot.png | 0
Dcontent/sysarch-notes/Memory locations & addresses.html | 4----
Acontent/sysarch-notes/Memory locations & addresses.md | 24++++++++++++++++++++++++
Dcontent/sysarch-notes/Memory operations & instructions.html | 4----
Acontent/sysarch-notes/Memory operations & instructions.md | 49+++++++++++++++++++++++++++++++++++++++++++++++++
Dcontent/sysarch-notes/Memory types.html | 4----
Acontent/sysarch-notes/Memory types/index.md | 69+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Rcontent/sysarch-notes/Memory types.resources/screenshot_2.png -> content/sysarch-notes/Memory types/screenshot-48.png | 0
Rcontent/sysarch-notes/Memory types.resources/screenshot.png -> content/sysarch-notes/Memory types/screenshot-49.png | 0
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Dcontent/sysarch-notes/Multiplexers.html | 4----
Acontent/sysarch-notes/Multiplexers/index.md | 9+++++++++
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Rcontent/sysarch-notes/Multiplexers.resources/screenshot_1.png -> content/sysarch-notes/Multiplexers/screenshot-35.png | 0
Dcontent/sysarch-notes/Multiplication of signed integers.html | 4----
Acontent/sysarch-notes/Multiplication of signed integers/index.md | 70++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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Rcontent/sysarch-notes/Multiplication of signed integers.resources/screenshot_4.png -> content/sysarch-notes/Multiplication of signed integers/screenshot-18.png | 0
Dcontent/sysarch-notes/Multiplying_dividing floats.html | 4----
Rcontent/sysarch-notes/Multiplying_dividing floats.resources/Scannable Document on 5 Dec 2017 at 23_21_25.png -> content/sysarch-notes/Multiplying_dividing floats/doc.png | 0
Acontent/sysarch-notes/Multiplying_dividing floats/index.md | 17+++++++++++++++++
Dcontent/sysarch-notes/Multithreading.html | 4----
Acontent/sysarch-notes/Multithreading.md | 27+++++++++++++++++++++++++++
Dcontent/sysarch-notes/Numeric representations of data types.html | 112-------------------------------------------------------------------------------
Acontent/sysarch-notes/Numeric representations of data types/index.md | 87+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Rcontent/sysarch-notes/Numeric representations of data types.resources/screenshot.png -> content/sysarch-notes/Numeric representations of data types/screenshot-39.png | 0
Dcontent/sysarch-notes/Parallel programming.html | 4----
Acontent/sysarch-notes/Parallel programming.md | 20++++++++++++++++++++
Dcontent/sysarch-notes/Performance considerations.html | 4----
Acontent/sysarch-notes/Performance considerations.md | 18++++++++++++++++++
Dcontent/sysarch-notes/Positional numbering system.html | 4----
Dcontent/sysarch-notes/Positional numbering system.resources/Page 28 - Livescribe 3 Starter Notebook.pdf | 0
Dcontent/sysarch-notes/Positional numbering system.resources/Page 29 - Livescribe 3 Starter Notebook.pdf | 0
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Dcontent/sysarch-notes/Positional numbering system.resources/screenshot_1.png | 0
Dcontent/sysarch-notes/Program-controlled I_O.html | 4----
Acontent/sysarch-notes/Program-controlled I_O/index.md | 44++++++++++++++++++++++++++++++++++++++++++++
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Dcontent/sysarch-notes/Registers and Shift Registers.html | 4----
Acontent/sysarch-notes/Registers and Shift Registers/index.md | 16++++++++++++++++
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Dcontent/sysarch-notes/Representation of data.html | 4----
Acontent/sysarch-notes/Representation of data.md | 68++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Dcontent/sysarch-notes/Shared-memory multiprocessors.html | 4----
Acontent/sysarch-notes/Shared-memory multiprocessors/index.md | 50++++++++++++++++++++++++++++++++++++++++++++++++++
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Dcontent/sysarch-notes/Subroutines & the Stack.html | 4----
Acontent/sysarch-notes/Subroutines & the Stack/index.md | 47+++++++++++++++++++++++++++++++++++++++++++++++
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Dcontent/sysarch-notes/Superscalar operation.html | 4----
Acontent/sysarch-notes/Superscalar operation/index.md | 31+++++++++++++++++++++++++++++++
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Dcontent/sysarch-notes/Synthesis of logic functions.html | 4----
Acontent/sysarch-notes/Synthesis of logic functions/index.md | 54++++++++++++++++++++++++++++++++++++++++++++++++++++++
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Acontent/sysarch-notes/Take notes on.md | 11+++++++++++
Dcontent/sysarch-notes/The Basic Concept.html | 4----
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Dcontent/sysarch-notes/Universal gates.html | 4----
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Dcontent/sysarch-notes/Vector (SIMD) processing & GPUs.html | 4----
Acontent/sysarch-notes/Vector (SIMD) processing & GPUs.md | 26++++++++++++++++++++++++++
Acontent/sysarch-notes/_index.md | 115+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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Acontent/sysarch-notes/positional-numbering-system.md | 36++++++++++++++++++++++++++++++++++++
Dcontent/sysarch-notes/sitewide.css | 31-------------------------------
183 files changed, 1840 insertions(+), 898 deletions(-)

diff --git a/content/_index.md b/content/_index.md @@ -49,7 +49,7 @@ title = "Alex's university course notes" * [Introduction to Programming in C++](cpp-notes) * [Computational thinking](compthink-notes) -* [Systems architecture](https://thezeroalpha.github.io/sysarch-notes) +* [Systems architecture](sysarch-notes) * [Physical Computing](physcomp-notes) * [Logic & sets](logicsets-notes/) * [Web tech](webtech-notes) diff --git a/content/sysarch-notes/Accessing I_O devices.html b/content/sysarch-notes/Accessing I_O devices.html @@ -1,3 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="-0.2330510020256042"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-12-17 11:57:04 AM +0000"/><meta name="latitude" content="52.37362192175261"/><meta name="longitude" content="4.836259202323236"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-12-17 1:34:09 PM +0000"/><title>Accessing I/O devices</title></head><body><div>I/O means input/output — e.g. input from switch/microphone, output to speaker/motor/whatever</div><div><br/></div><div>components of a computer system communicate through interconnection network (circuits)</div><div>each I/O device appears to processor as addressable locations</div><div>implemented as bit storage flip-flops in the form of registers (“I/O registers”)</div><div>I/O devices and memory share same address space — “memory-mapped I/O)</div><div>this means that any instruction which accesses memory can access the device</div><div><br/></div><div><span style="font-weight: bold;">I/O device interface</span></div><div>a device is connected to interconnection network using a circuit — “device interface”</div><div>provides means for data transfer, exchange of status &amp; control info</div><div><br/></div></body></html>- \ No newline at end of file diff --git a/content/sysarch-notes/Accessing I_O devices.md b/content/sysarch-notes/Accessing I_O devices.md @@ -0,0 +1,20 @@ ++++ +title = 'Accessing I/O Devices' ++++ +# Accessing I/O Devices +I/O means input/output — e.g. input from switch/microphone, output to speaker/motor/whatever + +components of a computer system communicate through interconnection network (circuits) + +each I/O device appears to processor as addressable locations + +implemented as bit storage flip-flops in the form of registers (“I/O registers”) + +I/O devices and memory share same address space — “memory-mapped I/O) +this means that any instruction which accesses memory can access the device + +## I/O device interface + +a device is connected to interconnection network using a circuit — “device interface” + +provides means for data transfer, exchange of status & control info diff --git a/content/sysarch-notes/Adding_subtracting floating point values.html b/content/sysarch-notes/Adding_subtracting floating point values.html @@ -1,3 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="0.005558321252465248"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-12-05 9:59:53 PM +0000"/><meta name="latitude" content="52.37364100782783"/><meta name="longitude" content="4.8361598895452"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-12-05 10:08:07 PM +0000"/><title>Adding/subtracting floating point values</title></head><body><div><ol><li>Choose a number with the smaller exponent and move its mantissa right to make the exponents equal.</li><li>Exponent of the result is the same as the larger exponent.</li><li>Add/subtract the mantissas, determine sign of the result.</li><li>Normalise the resulting values.</li></ol><div><br/></div></div><div>Example:</div><div><br/></div><div><img src="Adding_subtracting%20floating%20point%20values.resources/Scannable%20Document%20on%205%20Dec%202017%20at%2023_07_42.png" height="1346" width="2056"/></div><div><br/></div></body></html>- \ No newline at end of file diff --git a/content/sysarch-notes/Adding_subtracting floating point values.resources/Scannable Document on 5 Dec 2017 at 23_07_42.png b/content/sysarch-notes/Adding_subtracting floating point values/doc.png Binary files differ. diff --git a/content/sysarch-notes/Adding_subtracting floating point values/index.md b/content/sysarch-notes/Adding_subtracting floating point values/index.md @@ -0,0 +1,12 @@ ++++ +title = 'Adding/subtracting floating point values' ++++ +# Adding/subtracting floating point values +1. Choose a number with the smaller exponent and move its mantissa right to make the exponents equal. +2. Exponent of the result is the same as the larger exponent. +3. Add/subtract the mantissas, determine sign of the result. +4. Normalise the resulting values. + +Example: + +![Scannable Document on 5 Dec 2017 at 23_07_42.png](doc.png) diff --git a/content/sysarch-notes/Addition & subtraction with signed integers.html b/content/sysarch-notes/Addition & subtraction with signed integers.html @@ -1,3 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="-1.015779376029968"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-12-05 4:15:58 PM +0000"/><meta name="latitude" content="52.33179173588104"/><meta name="longitude" content="4.869868269056413"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-12-05 9:49:51 PM +0000"/><title>Addition &amp; subtraction with signed integers</title></head><body><div>Just like with base-10 numbers, but you carry if you have more than the binary version of 1.<br/></div><div>To add (2’s complement): add bitwise, ignoring the leftmost carry-out.</div><div>To subtract (2’s complement): for X-Y, form 2’s complement of Y and then add.</div><div><br/></div><div><img src="Addition%20&amp;%20subtraction%20with%20signed%20integers.resources/screenshot.png" height="159" width="420"/>         <img src="Addition%20&amp;%20subtraction%20with%20signed%20integers.resources/screenshot_1.png" height="117" width="143"/><br/></div><div><br/></div><div>An overflow happens when both terms have the same sign and the result has a different sign.</div><div>In 1’s complement, the carry-out can’t be ignored — if it’s 0, the result is correct; if it’s 1, a 1 has to be added to the result.</div><div>You can stick the same value into more bits by repeating the leftmost digit.</div></body></html>- \ No newline at end of file diff --git a/content/sysarch-notes/Addition & subtraction with signed integers/index.md b/content/sysarch-notes/Addition & subtraction with signed integers/index.md @@ -0,0 +1,17 @@ ++++ +title = 'Addition & subtraction with signed integers' ++++ +# Addition & subtraction with signed integers +Just like with base-10 numbers, but you carry if you have more than the binary version of 1. + +To add (2’s complement): add bitwise, ignoring the leftmost carry-out. + +To subtract (2’s complement): for X-Y, form 2’s complement of Y and then add. + +![screenshot.png](screenshot-2.png) ![screenshot.png](screenshot-1.png) + +An overflow happens when both terms have the same sign and the result has a different sign. + +In 1’s complement, the carry-out can’t be ignored — if it’s 0, the result is correct; if it’s 1, a 1 has to be added to the result. + +You can stick the same value into more bits by repeating the leftmost digit. diff --git a/content/sysarch-notes/Addition & subtraction with signed integers.resources/screenshot_1.png b/content/sysarch-notes/Addition & subtraction with signed integers/screenshot-1.png Binary files differ. diff --git a/content/sysarch-notes/Addition & subtraction with signed integers.resources/screenshot.png b/content/sysarch-notes/Addition & subtraction with signed integers/screenshot-2.png Binary files differ. diff --git a/content/sysarch-notes/Addition_subtraction logic unit.html b/content/sysarch-notes/Addition_subtraction logic unit.html @@ -1,3 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="-0.6985639929771423"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-12-05 4:39:55 PM +0000"/><meta name="latitude" content="52.33421727619561"/><meta name="longitude" content="4.867580131602151"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-12-05 5:03:41 PM +0000"/><title>Addition/subtraction logic unit</title></head><body><div><b>Adders</b></div><div>A half adder takes two inputs, produces sum and carry-out.</div><div>A full adder also takes a carry-in.</div><div><br/></div><div>You can easily get this from a truth table:</div><div><img src="Addition_subtraction%20logic%20unit.resources/screenshot.png" height="56" width="355"/></div><div><br/></div><div>You can make a circuit out of this. Inputs are x, y, and carry. Carry out is c<sub>i+1</sub>:</div><div><table style="border-collapse: collapse; min-width: 100%;"><colgroup><col style="width: 201px;"/><col style="width: 335px;"/></colgroup><tbody><tr><td style="border: 1px solid rgb(219, 219, 219); background-color: rgb(255, 255, 255); width: 201px; padding: 8px;"><div>Sum:</div><div><img src="Addition_subtraction%20logic%20unit.resources/screenshot_3.png" height="104" width="179"/></div></td><td style="border: 1px solid rgb(219, 219, 219); background-color: rgb(255, 255, 255); width: 335px; padding: 8px;"><div>Carry:</div><div><img src="Addition_subtraction%20logic%20unit.resources/screenshot_4.png" height="183" width="251"/></div></td></tr></tbody></table><div><br/></div></div><div>That’s represented by the symbol:</div><div><img src="Addition_subtraction%20logic%20unit.resources/Screen%20Shot%202017-12-05%20at%205.56.28%20PM.png" height="190" width="241"/></div><div><br/></div><div>If you want to add n bits, you stick a bunch of them together and make an <i>n</i>-bit ripple-carry adder. x<sub>n-1</sub> and y<sub>n-1</sub> are the sign bits:</div><div><br/></div><div><img src="Addition_subtraction%20logic%20unit.resources/screenshot_1.png" height="219" width="620"/></div><div><br/></div><div><br/></div><div><b>Detecting overflow</b></div><div>Remember that the final carry out is not a part of the result.</div><div>It’s an overflow when:</div><div><ul><li>the sign of the sum is different from the sign of the summands</li><li>or the carry-out bits are different</li></ul><div><br/></div></div><div>Two logical expressions for detecting overflow (either works):</div><div><img src="Addition_subtraction%20logic%20unit.resources/466215F1-2DA6-4029-9FB6-43499ABD7D87.png" height="33" width="298"/></div><div><img src="Addition_subtraction%20logic%20unit.resources/screenshot_2.png" height="17" width="68"/></div><div><br/></div><div><br/></div><div><br/></div></body></html>- \ No newline at end of file diff --git a/content/sysarch-notes/Addition_subtraction logic unit.resources/466215F1-2DA6-4029-9FB6-43499ABD7D87.png b/content/sysarch-notes/Addition_subtraction logic unit/a5b4b0e66c6d8e53ab1bfbcf8f5c2d49.png Binary files differ. diff --git a/content/sysarch-notes/Addition_subtraction logic unit/index.md b/content/sysarch-notes/Addition_subtraction logic unit/index.md @@ -0,0 +1,39 @@ ++++ +title = 'Addition/subtraction logic unit' +template = 'page-math.html' ++++ +# Addition/subtraction logic unit +## Adders +A half adder takes two inputs, produces sum and carry-out. + +A full adder also takes a carry-in. + +You can easily get this from a truth table: + +![screenshot.png](screenshot-52.png) + +You can make a circuit out of this. Inputs are x, y, and carry. Carry out is $c_{i+1}$: + +| Sum | Carry | +| --- | --- | +| ![screenshot.png](screenshot-54.png) | ![screenshot.png](screenshot-51.png) | + +That’s represented by the symbol: + +![Screen Shot](shot.png) + +If you want to add n bits, you stick a bunch of them together and make an *n*-bit ripple-carry adder. $x_{n-1}$ and $y_{n-1}$ are the sign bits: + +![screenshot.png](screenshot-55.png) + +## Detecting overflow +Remember that the final carry out is not a part of the result. +It’s an overflow when: + +- the sign of the sum is different from the sign of the summands +- or the carry-out bits are different + +Two logical expressions for detecting overflow (either works): + +![](a5b4b0e66c6d8e53ab1bfbcf8f5c2d49.png) +![screenshot.png](screenshot-53.png) diff --git a/content/sysarch-notes/Addition_subtraction logic unit.resources/screenshot_4.png b/content/sysarch-notes/Addition_subtraction logic unit/screenshot-51.png Binary files differ. diff --git a/content/sysarch-notes/Addition_subtraction logic unit.resources/screenshot.png b/content/sysarch-notes/Addition_subtraction logic unit/screenshot-52.png Binary files differ. diff --git a/content/sysarch-notes/Addition_subtraction logic unit.resources/screenshot_2.png b/content/sysarch-notes/Addition_subtraction logic unit/screenshot-53.png Binary files differ. diff --git a/content/sysarch-notes/Addition_subtraction logic unit.resources/screenshot_3.png b/content/sysarch-notes/Addition_subtraction logic unit/screenshot-54.png Binary files differ. diff --git a/content/sysarch-notes/Addition_subtraction logic unit.resources/screenshot_1.png b/content/sysarch-notes/Addition_subtraction logic unit/screenshot-55.png Binary files differ. diff --git a/content/sysarch-notes/Addition_subtraction logic unit.resources/Screen Shot 2017-12-05 at 5.56.28 PM.png b/content/sysarch-notes/Addition_subtraction logic unit/shot.png Binary files differ. diff --git a/content/sysarch-notes/Addressing modes.html b/content/sysarch-notes/Addressing modes.html @@ -1,3 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="-0.3418765664100647"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-12-11 6:41:09 PM +0000"/><meta name="latitude" content="52.3736617734729"/><meta name="longitude" content="4.836225185090218"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-12-11 10:40:42 PM +0000"/><title>Addressing modes</title></head><body><div>addressing modes: ways of specifying locations of instruction operands</div><div><br/></div><div>Summary of RISC-type addressing modes:</div><div><br/></div><div><img src="Addressing%20modes.resources/screenshot.png" height="354" width="629"/><br/></div><div><br/></div><div><br/></div><div><span style="font-weight: bold;">Modes</span></div><div><div>Provide operand/address explicitly:</div><ul><li>Register — operand is contents of processor register, name of register is given in instruction</li><li>Absolute — operand is in memory location, address of location is given in instruction</li><li>Immediate — operand is given explicitly in instruction (use <span style="font-style: italic;"># </span>or <span style="font-style: italic;">$ </span>to indicate that it is an immediate operand)</li></ul><div><br/></div></div><div>Provide information from effective address:</div><div><ul><li>Indirect — effective address of operand is in register, register is given in instruction (pointer-type). use parentheses ()</li><li>Index — effective address of operand is generated by adding a constant to contents of register</li></ul></div><div><br/></div><div>when specifying an offset in index, the offset can be either positive or negative. means the number of bytes to move.</div></body></html>- \ No newline at end of file diff --git a/content/sysarch-notes/Addressing modes/index.md b/content/sysarch-notes/Addressing modes/index.md @@ -0,0 +1,23 @@ ++++ +title = 'Addressing modes' ++++ +# Addressing modes +addressing modes: ways of specifying locations of instruction operands + +Summary of RISC-type addressing modes: + +![screenshot.png](screenshot-7.png) + +## Modes +Provide operand/address explicitly: + +- Register — operand is contents of processor register, name of register is given in instruction +- Absolute — operand is in memory location, address of location is given in instruction +- Immediate — operand is given explicitly in instruction (use `#`or `$`to indicate that it is an immediate operand) + +Provide information from effective address: + +- Indirect — effective address of operand is in register, register is given in instruction (pointer-type). use parentheses `()` +- Index — effective address of operand is generated by adding a constant to contents of register + +when specifying an offset in index, the offset can be either positive or negative. means the number of bytes to move. diff --git a/content/sysarch-notes/Addressing modes.resources/screenshot.png b/content/sysarch-notes/Addressing modes/screenshot-7.png Binary files differ. diff --git a/content/sysarch-notes/Assembly.html b/content/sysarch-notes/Assembly.html @@ -1,3 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="0"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-11-19 9:25:23 PM +0000"/><meta name="latitude" content="52.37360283034186"/><meta name="longitude" content="4.836072408511082"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-11-20 7:47:22 PM +0000"/><title>Assembly</title></head><body><div>symbolic notation for machine language, improves readability</div><div>two syntaxes — Intel and AT&amp;T</div><div><ul><li>Intel: </li><ul><li>order</li><ul><li>operation destination source</li><li>e.g. mov rax, 5</li><li>just like a=5</li></ul><li>no decorations</li></ul><li>AT&amp;T:</li><ul><li>extra decorations like % in front of registers and $ in front of literal values</li><li>not very readable</li><li>order such as: mov 5, %rax</li></ul></ul><div><br/></div></div><div><br/></div><div>First four arguments: %rax, %rdi, %rsi, %rdx</div><div>When you write a subroutine, push the base pointer. Then set the base pointer to the stack pointer.</div><div>At the end of the subroutine, set the stack pointer to the base pointer. Then pop the base pointer. Then ret.</div><div><br/></div><div>Syscall 60 is exit, 1 is write, 0 is read.</div><div>1 is stdout, 0 is stdin, 2 is stderr.</div><div><br/></div><div>Registers store addresses. Parentheses are used to access value at address.</div><div><ul/></div><div><br/></div></body></html>- \ No newline at end of file diff --git a/content/sysarch-notes/Assembly.md b/content/sysarch-notes/Assembly.md @@ -0,0 +1,27 @@ ++++ +title = 'Assembly' ++++ +symbolic notation for machine language, improves readability +two syntaxes — Intel and AT&T + +- Intel: + - order + - operation destination source + - e.g. mov rax, 5 + - just like a=5 + - no decorations +- AT&T: + - extra decorations like % in front of registers and $ in front of literal values + - not very readable + - order such as: mov 5, %rax + +First four arguments: %rax, %rdi, %rsi, %rdx + +When you write a subroutine, push the base pointer. Then set the base pointer to the stack pointer. + +At the end of the subroutine, set the stack pointer to the base pointer. Then pop the base pointer. Then ret. + +Syscall 60 is exit, 1 is write, 0 is read. +1 is stdout, 0 is stdin, 2 is stderr. + +Registers store addresses. Parentheses are used to access value at address. diff --git a/content/sysarch-notes/Basic concepts.html b/content/sysarch-notes/Basic concepts.html @@ -1,3 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="-0.09754352271556854"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-12-17 1:39:53 PM +0000"/><meta name="latitude" content="52.37355729316155"/><meta name="longitude" content="4.836194589138463"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-12-17 2:10:55 PM +0000"/><title>Basic concepts</title></head><body><div>maximum size of memory depends on the addressing scheme</div><div>memory access time — time elapsed between start of transfer of word of data and completion</div><div>memory cycle time — minimum time delay required between initiation of two successive memory operations</div><div><br/></div><div>RAM (random-access memory) — memory where access time to any location is the same (compare to serial access)</div><div><br/></div><div><b>Cache &amp; virtual memory</b></div><div>memory access time is the bottleneck in the system. options to speed this up: </div><div><ul><li>cache memory — small, fast memory between main memory and processor<br/></li><li>virtual memory — only active portions of program are in main memory, remainder is on a secondary storage device</li></ul><div><br/></div></div><div>data is transferred between memories in blocks involving tens to thousands of words</div><div><br/></div></body></html>- \ No newline at end of file diff --git a/content/sysarch-notes/Basic concepts.md b/content/sysarch-notes/Basic concepts.md @@ -0,0 +1,19 @@ ++++ +title = 'Basic concepts' ++++ +# Basic concepts +maximum size of memory depends on the addressing scheme + +memory access time — time elapsed between start of transfer of word of data and completion + +memory cycle time — minimum time delay required between initiation of two successive memory operations + +RAM (random-access memory) — memory where access time to any location is the same (compare to serial access) + +## Cache & virtual memory +memory access time is the bottleneck in the system. options to speed this up: + +- cache memory — small, fast memory between main memory and processor +- virtual memory — only active portions of program are in main memory, remainder is on a secondary storage device + +data is transferred between memories in blocks involving tens to thousands of words diff --git a/content/sysarch-notes/Basic logic gates.html b/content/sysarch-notes/Basic logic gates.html @@ -1,3 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="-0.08564221858978271"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-11-08 1:02:23 PM +0000"/><meta name="latitude" content="52.33349196807026"/><meta name="longitude" content="4.867801900572072"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-11-09 1:02:24 PM +0000"/><title>Basic logic gates</title></head><body><div>Logic gates are transistor-based components. Here are the four basic nes.</div><div><span style="font-weight: bold;"><br/></span></div><div><span style="font-weight: bold;">NOT (complement)</span></div><div>for a variable x,</div><div>x̄ = 1-x</div><div>∴ x + x̄ = 1</div><div><br/></div><div><img src="Basic%20logic%20gates.resources/screenshot_3.png" height="90" width="241"/><br/></div><div><br/></div><div><span style="font-weight: bold;">OR (union)</span></div><div>OR function (+) has value 1 if any of inputs has value 1.</div><div><br/></div><div><img src="Basic%20logic%20gates.resources/screenshot_1.png" height="89" width="277"/><br/></div><div>Properties:</div><div>1 + x = 1</div><div>0 + x = x</div><div><br/></div><div><span style="font-weight: bold;">AND (intersection)</span></div><div>AND function (⋅) has value 1 if all inputs have value 1.</div><div>NOTE: the operator ‘⋅’ is often omitted!</div><div><br/></div><div><img src="Basic%20logic%20gates.resources/screenshot.png" height="87" width="273"/><br/></div><div><br/></div><div>Properties:</div><div>x₁ ⋅ x₂ = x₂ ⋅ x₁</div><div>1 ⋅ x = x</div><div><br/></div><div><span style="font-weight: bold;">XOR (exclusive or)</span></div><div>XOR function (⨁) has value 1 if one of inputs has value 1.</div><div><img src="Basic%20logic%20gates.resources/screenshot_2.png" height="84" width="280"/><br/></div><div><br/></div><div>x₁ ⨁ x₂ = x₂ ⨁ x₁</div><div>1 ⨁ x = x̄</div><div>0 ⨁ x = x</div><div><br/></div><div>How an XOR gate is built and functions:</div><div><br/></div><div><img src="Basic%20logic%20gates.resources/circuit.gif" height="190" width="480"/><br/></div><div><br/></div></body></html>- \ No newline at end of file diff --git a/content/sysarch-notes/Basic logic gates.resources/circuit.gif b/content/sysarch-notes/Basic logic gates/circuit.gif Binary files differ. diff --git a/content/sysarch-notes/Basic logic gates/index.md b/content/sysarch-notes/Basic logic gates/index.md @@ -0,0 +1,46 @@ ++++ +title = 'Basic logic gates' ++++ +# Basic logic gates +Logic gates are transistor-based components. Here are the four basic ones. + +## NOT (complement) + +for a variable x, +x̄ = 1-x +∴ x + x̄ = 1 + +![screenshot.png](screenshot-28.png) + +## OR (union) +OR function (+) has value 1 if any of inputs has value 1. + +![screenshot.png](screenshot-26.png) + +Properties: +- 1 + x = 1 +- 0 + x = x + +## AND (intersection) +AND function (⋅) has value 1 if all inputs have value 1. + +NOTE: the operator ‘⋅’ is often omitted! + +![screenshot.png](screenshot-29.png) + +Properties: +- x₁ ⋅ x₂ = x₂ ⋅ x₁ +- 1 ⋅ x = x + +## XOR (exclusive or) +XOR function (⨁) has value 1 if one of inputs has value 1. + +![screenshot.png](screenshot-27.png) + +- x₁ ⨁ x₂ = x₂ ⨁ x₁ +- 1 ⨁ x = x̄ +- 0 ⨁ x = x + +How an XOR gate is built and functions: + +![circuit.gif](circuit.gif) diff --git a/content/sysarch-notes/Basic logic gates.resources/screenshot_1.png b/content/sysarch-notes/Basic logic gates/screenshot-26.png Binary files differ. diff --git a/content/sysarch-notes/Basic logic gates.resources/screenshot_2.png b/content/sysarch-notes/Basic logic gates/screenshot-27.png Binary files differ. diff --git a/content/sysarch-notes/Basic logic gates.resources/screenshot_3.png b/content/sysarch-notes/Basic logic gates/screenshot-28.png Binary files differ. diff --git a/content/sysarch-notes/Basic logic gates.resources/screenshot.png b/content/sysarch-notes/Basic logic gates/screenshot-29.png Binary files differ. diff --git a/content/sysarch-notes/Basic processing unit.html b/content/sysarch-notes/Basic processing unit.html @@ -1,3 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="2.037073373794556"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-11-23 3:08:56 PM +0000"/><meta name="latitude" content="52.33301536382147"/><meta name="longitude" content="4.865530882137468"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-11-30 2:10:04 PM +0000"/><title>Basic processing unit</title></head><body><div><span style="font-weight: bold;">Organisation and basic processing cycle</span></div><div>Execution of complete instruction:</div><div><ol><li>Fetch instruction</li><ul><li>fetch instruction pointed to by PC, put it into IR (instruction register)</li><li>increment PC by number of bytes</li><li>decode IR and execute instruction specified in IR</li></ul><li>Fetch operand</li><li>Perform operation</li><ul><li>use memory operand / NOP</li></ul><li>Store result</li></ol><div><br/></div></div><div><br/></div><div>Components:</div><div><ul><li>CPU bus in the middle — means of communication between different components</li><ul><li>connects every pair of components</li><li>bus width is based on the size of the word (bits), e.g. 32 or 64 depending on the ISA</li><li>bus can only transport that many bits max</li><li>every component can read at the same time</li><li>only one component can write at a certain time</li></ul><li>PC (program counter) — counts instructions, notes which is next</li><li>Processor-memory interface — registers</li><ul><li>Y register — internal, cannot be accessed</li><li>MAR (memory address register) — stores location of various data in memory</li><li>MDR (memory data register) — stores values (data) to be stored</li><li>IR (instruction register) — stores the next instruction</li></ul><li>Decoder — changes (decodes) an instruction into signals</li><li>Register file (R0, R1, R2,…)</li><ul><li>package multiple registers together</li><li>add single gates for input and output -&gt; lower energy requirements</li><li>but with this, only one register can read/write the bus at a time.</li><li>so add another bus ¯\_(ツ)_/¯ energy requirement is the limit</li></ul><li>ALU — computes stuff</li></ul></div><div><br/></div><div>Register gating:</div><div><ul><li>controls who can access the bus</li><li>Put gates before each component to control input/output</li></ul><div><br/></div></div><div>Register transfer (e.g. R1 to R3 — all happens at once):</div><div><ol><li>Addr_out = R1</li><li>R_out</li><li>Addr_in=R3</li><li>R_in</li></ol><div><br/></div></div><div>Load from memory:</div><div><ol><li>Ri_out, MAR_in, read</li><li>MDR_inE, WMFC</li><li>MDR_out, Ri_in</li></ol><div><br/></div></div><div>Store to memory:</div><div><ol><li>Ri_out, MAR_in</li><li>Rj_out, MDR_in, write</li><li>MDR_outE, WMFC</li></ol></div><div><ol/></div><div><br/></div><div><br/></div></body></html>- \ No newline at end of file diff --git a/content/sysarch-notes/Basic processing unit.md b/content/sysarch-notes/Basic processing unit.md @@ -0,0 +1,61 @@ ++++ +title = 'Basic processing unit' ++++ +# Basic processing unit +## Organisation and basic processing cycle +Execution of complete instruction: +1. Fetch instruction + + - fetch instruction pointed to by PC, put it into IR (instruction register) + - increment PC by number of bytes + - decode IR and execute instruction specified in IR + +2. Fetch operand +3. Perform operation + + - use memory operand / NOP + +4. Store result + +Components: + +- CPU bus in the middle — means of communication between different components + - connects every pair of components + - bus width is based on the size of the word (bits), e.g. 32 or 64 depending on the ISA + - bus can only transport that many bits max + - every component can read at the same time + - only one component can write at a certain time +- PC (program counter) — counts instructions, notes which is next +- Processor-memory interface — registers + - Y register — internal, cannot be accessed + - MAR (memory address register) — stores location of various data in memory + - MDR (memory data register) — stores values (data) to be stored + - IR (instruction register) — stores the next instruction +- Decoder — changes (decodes) an instruction into signals +- Register file (R0, R1, R2,…) + - package multiple registers together + - add single gates for input and output -> lower energy requirements + - but with this, only one register can read/write the bus at a time. + - so add another bus `¯\_(ツ)_/¯` energy requirement is the limit +- ALU — computes stuff + +Register gating: + +- controls who can access the bus +- Put gates before each component to control input/output + +Register transfer (e.g. R1 to R3 — all happens at once): +1. Addr_out = R1 +2. R_out +3. Addr_in=R3 +4. R_in + +Load from memory: +1. Ri_out, MAR_in, read +2. MDR_inE, WMFC +3. MDR_out, Ri_in + +Store to memory: +1. Ri_out, MAR_in +2. Rj_out, MDR_in, write +3. MDR_outE, WMFC diff --git a/content/sysarch-notes/Branch delays.html b/content/sysarch-notes/Branch delays.html @@ -1,3 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="-0.2646212577819824"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-12-18 12:58:58 PM +0000"/><meta name="latitude" content="52.37360486727292"/><meta name="longitude" content="4.8363388956229"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-12-18 1:41:48 PM +0000"/><title>Branch delays</title></head><body><div><b>Unconditional branches</b></div><div>the two instructions that are fetched during decode and compute of first instruction (a branch) have to be discarded</div><div>this two cycle-delay — “branch penalty”</div><div><br/></div><div><img src="Branch%20delays.resources/screenshot_1.png" height="492" width="739"/></div><div><br/></div><div>to reduce the penalty, branch target address must be computed earlier than pipeline — in the decode stage</div><div>this reduces the penalty to one cycle:</div><div><br/></div><div><img src="Branch%20delays.resources/screenshot_2.png" height="397" width="678"/></div><div><br/></div><div>this needs hardware modification — PC has to be incremented in every cycle, and a second adder is needed in decode stage to compute branch target address for every instruction</div><div><br/></div><div><b>Conditional branches</b></div><div>branch condition must be tested as early as possible</div><div>comparator to test condition can be moved to decode stage</div><div>it would use values from register file outputs A and B directly</div><div><br/></div><div><b>Branch delay slot — compiler reorganises instructions</b></div><div>branch delays slot — the location that follows a branch instruction</div><div>compiler tries to find an instruction that it always executed, independent of whether or not the program branches</div><div>data dependencies must be preserved</div><div>if the compiler can find a useful instruction, there’s no branch penalty</div><div>otherwise, it NOPs out and there’s a penalty of one cycle</div><div><br/></div><div><img src="Branch%20delays.resources/screenshot.png" height="586" width="490"/></div><div><br/></div><div><br/></div><div><b>Branch prediction</b></div><div>Static:</div><div><ul><li>assume branch will not be taken, fetch next instruction in sequential order<br/></li><li>simple, decent accuracy</li><li>processor can determine static prediction by checking sign of branch offset</li><li>other option — encoding of branch instruction can include a bit indicating whether prediction should be ‘take’ or ‘not taken’ (set by compiler)</li></ul><div><br/></div></div><div>Dynamic:</div><div><ul><li>use actual branch behaviour</li><li>processor assumes that next time an instruction is executed, branch decision is likely to be the same as last time</li><li>keep more information about execution history, such as four states (strongly taken, likely taken, likely not taken, strongly not taken)</li><li>keep a branch target buffer</li><ul><li>identifies branch instructions by their addresses</li><li>in the form of lookup table</li><li>contains: address of branch instruction, one/two state bits for branch prediction algorithm (outcome), branch target address</li></ul></ul></div><div><br/></div></body></html>- \ No newline at end of file diff --git a/content/sysarch-notes/Branch delays/index.md b/content/sysarch-notes/Branch delays/index.md @@ -0,0 +1,53 @@ ++++ +title = 'Branch delays' ++++ +# Branch delays +## Unconditional branches + +the two instructions that are fetched during decode and compute of first instruction (a branch) have to be discarded + +this two cycle-delay — “branch penalty” + +![screenshot.png](screenshot-40.png) + +to reduce the penalty, branch target address must be computed earlier than pipeline — in the decode stage + +this reduces the penalty to one cycle: + +![screenshot.png](screenshot-41.png) + +this needs hardware modification — PC has to be incremented in every cycle, and a second adder is needed in decode stage to compute branch target address for every instruction + +## Conditional branches +branch condition must be tested as early as possible +comparator to test condition can be moved to decode stage +it would use values from register file outputs A and B directly + +## Branch delay slot — compiler reorganises instructions +branch delays slot — the location that follows a branch instruction + +compiler tries to find an instruction that it always executed, independent of whether or not the program branches + +data dependencies must be preserved +if the compiler can find a useful instruction, there’s no branch penalty +otherwise, it NOPs out and there’s a penalty of one cycle + +![screenshot.png](screenshot-42.png) + +## Branch prediction +Static: + +- assume branch will not be taken, fetch next instruction in sequential order +- simple, decent accuracy +- processor can determine static prediction by checking sign of branch offset +- other option — encoding of branch instruction can include a bit indicating whether prediction should be ‘take’ or ‘not taken’ (set by compiler) + +Dynamic: + +- use actual branch behaviour +- processor assumes that next time an instruction is executed, branch decision is likely to be the same as last time +- keep more information about execution history, such as four states (strongly taken, likely taken, likely not taken, strongly not taken) +- keep a branch target buffer + - identifies branch instructions by their addresses + - in the form of lookup table + - contains: address of branch instruction, one/two state bits for branch prediction algorithm (outcome), branch target address diff --git a/content/sysarch-notes/Branch delays.resources/screenshot_1.png b/content/sysarch-notes/Branch delays/screenshot-40.png Binary files differ. diff --git a/content/sysarch-notes/Branch delays.resources/screenshot_2.png b/content/sysarch-notes/Branch delays/screenshot-41.png Binary files differ. diff --git a/content/sysarch-notes/Branch delays.resources/screenshot.png b/content/sysarch-notes/Branch delays/screenshot-42.png Binary files differ. diff --git a/content/sysarch-notes/Buses.html b/content/sysarch-notes/Buses.html @@ -1,3 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="0.2139492332935333"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-12-16 11:12:21 PM +0000"/><meta name="latitude" content="52.37346668956735"/><meta name="longitude" content="4.836244824703589"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-12-16 11:42:23 PM +0000"/><title>Buses</title></head><body><div><span style="font-weight: bold;">Bus Structure</span></div><div>bus — commonly used interconnection network between processor, memory, and I/O devices</div><div>three sets of lines (wires) to carry address, data, and control signals</div><div><ul><li>address lines — processor places address on it, decoders of all devices on the bus analyse it, the one that recognises the address responds to commands on control line</li><li>control lines — used by processor to request read/write</li><li>data lines — used for transferring requested data</li></ul></div><div><br/></div><div>when processor places address on address line, decoders of all devices on the bus analyse it</div><div>the device that recognises the address responds to the commands on the control lines</div><div><br/></div><div><span style="font-weight: bold;">Bus operation</span></div><div>bus protocol — set of rules governing how it’s used by various devices</div><div>rules are implemented by control signals</div><div>e.g. a R/W̄ control line — read when 1, write when 0</div><div><br/></div><div>if multiple devices request to access the bus, the decision is made by an arbiter circuit</div><div><br/></div><div>Synchronous bus: all devices get timing info from bus clock control line</div><div><ul><li>simple, but it’s got problems</li><li>transfer has to be done in one clock cycle, so clock period has to accommodate slowest component</li><li>processor can’t determine whether device actually responded</li><li>so many designs include control signals representing a response from a device</li></ul><div><img src="Buses.resources/screenshot.png" height="432" width="589"/><br/></div></div><div><br/></div><div>Asynchronous bus: based on use of a handshake protocol between master and slave (exchange of command and response signals)</div><div><br/></div><div><img src="Buses.resources/screenshot_1.png" height="456" width="647"/><br/></div><div><br/></div><div><br/></div></body></html>- \ No newline at end of file diff --git a/content/sysarch-notes/Buses/index.md b/content/sysarch-notes/Buses/index.md @@ -0,0 +1,39 @@ ++++ +title = 'Buses' ++++ +# Buses +## Bus Structure + +bus — commonly used interconnection network between processor, memory, and I/O devices + +three sets of lines (wires) to carry address, data, and control signals + +- address lines — processor places address on it, decoders of all devices on the bus analyse it, the one that recognises the address responds to commands on control line +- control lines — used by processor to request read/write +- data lines — used for transferring requested data + +when processor places address on address line, decoders of all devices on the bus analyse it + +the device that recognises the address responds to the commands on the control lines + +## Bus operation +bus protocol — set of rules governing how it’s used by various devices + +rules are implemented by control signals + +e.g. a R/W̄ control line — read when 1, write when 0 + +if multiple devices request to access the bus, the decision is made by an arbiter circuit + +Synchronous bus: all devices get timing info from bus clock control line + +- simple, but it’s got problems +- transfer has to be done in one clock cycle, so clock period has to accommodate slowest component +- processor can’t determine whether device actually responded +- so many designs include control signals representing a response from a device + +![screenshot.png](screenshot-30.png) + +Asynchronous bus: based on use of a handshake protocol between master and slave (exchange of command and response signals) + +![screenshot.png](screenshot-31.png) diff --git a/content/sysarch-notes/Buses.resources/screenshot.png b/content/sysarch-notes/Buses/screenshot-30.png Binary files differ. diff --git a/content/sysarch-notes/Buses.resources/screenshot_1.png b/content/sysarch-notes/Buses/screenshot-31.png Binary files differ. diff --git a/content/sysarch-notes/Cache coherence.html b/content/sysarch-notes/Cache coherence.html @@ -1,3 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="0.008051681332290173"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-12-20 8:52:44 PM +0000"/><meta name="latitude" content="52.37351596501021"/><meta name="longitude" content="4.836192148060309"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-12-20 9:33:06 PM +0000"/><title>Cache coherence</title></head><body><div>copies of shared data may be in several caches</div><div>when any processor writes to a shared variable its cache, other caches with a copy of that variable have to be informed of the change — cache coherence</div><div>whenever a block is in a shared state, the memory owns it</div><div><br/></div><div><b>Write-through protocol</b></div><div>two ways:</div><div><ul><li>update protocol — broadcast written data to caches of all processors in the system, each processor updates contents of affected cache</li><li>invalidation protocol — broadcast invalidation requests to all processors in the system</li></ul><div><br/></div></div><div><b>Write-back protocol</b></div><div>based on concept of ownership of a block of data in the memory</div><div>creates less traffic because writes only happen in cache (unlike write-through)</div><div><br/></div><div><ul><li>at the start, memory owns all blocks and retains ownership if a block is read<br/></li><li>writing to a new block: </li><ul><li>the requesting processor must become an exclusive owner of the block</li><li>all copies must be invalidated with a broadcast request</li></ul><li>reading a modified block</li><ul><li>it’s sent by the current owner to the processor and the memory, ending up with two copies in two caches and the memory</li><li>subsequent requests for the same block are serviced by the memory module.</li></ul><li>writing to a modified block</li><ul><li>current owner sends data to requesting processor, which becomes owner</li><li>old owner invalidates its cached copy</li><li>contents of memory are <u>not</u> updated, next request for the block is serviced by the new owner</li></ul></ul></div><div><br/></div><div><b>Snoopy caches</b></div><div>all transactions in a single-bus system occur through requests/responses on bus</div><div>snooping is observing all transactions on the bus through a controller circuit</div><div>if a processor broadcasts a read request for a block owned by a processor, the memory is not allowed to respond</div><div>the owner of the block snoops on the bus and sees the request, and asserts a signal on the bus that effectively tells the memory “hell nah bitch I got this”</div><div>then the owner broadcasts a copy of the block on the bus, marks its copy as unmodified, and the response is accepted by the processor that issued the read request.</div><div>the memory also reacquires ownership of the block and updates its copy (and its shared because there’s two copies in caches of two processors)</div><div>further requests are serviced by the memory.</div><div><br/></div><div>if two processors have copies and both try to write to the same cache at the same time:</div><div><ol><li>One of the processors gets to use the bus first, broadcasts an invalidation request, and becomes the owner</li><li>The other processor snoops and invalidates its copy</li><li>When other processor gets to use the bus, it broadcasts a read-exclusive request (read + invalidation request)</li><li>Owner snoops the read-exclusive request, provides a data response, and invalidates its copy (other processor becomes new owner)</li></ol><div><br/></div></div><div>an alternative in large shared-memory multiprocessors is directory-based cache coherence, where there are directories in each memory module which indicate which nodes can have copies of a given block</div><div>if a block is modified, the directory identifies node that is current owner</div><div><br/></div></body></html>- \ No newline at end of file diff --git a/content/sysarch-notes/Cache coherence.md b/content/sysarch-notes/Cache coherence.md @@ -0,0 +1,61 @@ ++++ +title = 'Cache coherence' ++++ +# Cache coherence +copies of shared data may be in several caches + +when any processor writes to a shared variable its cache, other caches with a copy of that variable have to be informed of the change — cache coherence + +whenever a block is in a shared state, the memory owns it + +## Write-through protocol +two ways: + +- update protocol — broadcast written data to caches of all processors in the system, each processor updates contents of affected cache +- invalidation protocol — broadcast invalidation requests to all processors in the system + +## Write-back protocol +based on concept of ownership of a block of data in the memory + +creates less traffic because writes only happen in cache (unlike write-through) + +- at the start, memory owns all blocks and retains ownership if a block is read +- writing to a new block: + - the requesting processor must become an exclusive owner of the block + - all copies must be invalidated with a broadcast request +- reading a modified block + - it’s sent by the current owner to the processor and the memory, ending up with two copies in two caches and the memory + - subsequent requests for the same block are serviced by the memory module. +- writing to a modified block + - current owner sends data to requesting processor, which becomes owner + - old owner invalidates its cached copy + - contents of memory are *not* updated, next request for the block is serviced by the new owner + +## Snoopy caches +all transactions in a single-bus system occur through requests/responses on bus + +snooping is observing all transactions on the bus through a controller circuit + +if a processor broadcasts a read request for a block owned by a processor, the memory is not allowed to respond + +the owner of the block snoops on the bus and sees the request, and asserts a signal on the bus that effectively tells the memory “hell nah bitch I got this” + +then the owner broadcasts a copy of the block on the bus, marks its copy as unmodified, and the response is accepted by the processor that issued the read request. + +the memory also reacquires ownership of the block and updates its copy (and its shared because there’s two copies in caches of two processors) + +further requests are serviced by the memory. + +if two processors have copies and both try to write to the same cache at the same time: + +1. One of the processors gets to use the bus first, broadcasts an invalidation request, and becomes the owner + +2. The other processor snoops and invalidates its copy + +3. When other processor gets to use the bus, it broadcasts a read-exclusive request (read + invalidation request) + +4. Owner snoops the read-exclusive request, provides a data response, and invalidates its copy (other processor becomes new owner) + +an alternative in large shared-memory multiprocessors is directory-based cache coherence, where there are directories in each memory module which indicate which nodes can have copies of a given block + +if a block is modified, the directory identifies node that is current owner diff --git a/content/sysarch-notes/Cache memory.html b/content/sysarch-notes/Cache memory.html @@ -1,3 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="-0.3490290641784668"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-12-17 6:39:12 PM +0000"/><meta name="latitude" content="52.37364222894153"/><meta name="longitude" content="4.836288522954751"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-12-17 7:12:48 PM +0000"/><title>Cache memory</title></head><body><div>very small, very fast</div><div>between processor and main memory, its there to be a wingman and make the main memory look good in front of the processor</div><div><br/></div><div>locality of reference — many instructions in localised areas of the program are executed repeatedly during some time period</div><div><ul><li>temporal — recently executed is likely to be executed again soon</li><li>spatial — instructions close to a recently executed instruction are likely to be executed again soon</li></ul></div><div><br/></div><div>basically, whenever some info is needed, it should be brought into the cache. and might as well grab data at adjacent addresses too.</div><div><br/></div><div>cache block/line — set of contiguous address locations of some size</div><div><br/></div><div>the mapping function specifies correspondence between main memory blocks and those in cache</div><div>replacement algorithm decides which blocks to remove to make space for a newly referenced word</div><div><br/></div><div>cache hits</div><div><ul><li>processor issues read/write requests</li><li>cache control circuitry determines if the requested word is in cache</li><li>if read hit, data is read from cache &amp; main memory is not involved</li><li>if write hit, two options:</li><ul><li>write-through — both cache and main memory are updated</li><ul/><li>write-back — update only cache location and mark block with an associated flag bit (dirty/modified bit), main memory is updated later</li></ul></ul><div><br/></div></div><div>cache misses:</div><div><ul><li>read miss — the block containing the requested word is copied from main memory into cache, then the word is forwarded to the processor</li><ul><li>load-through — alternative approach where word is sent to processor as soon as it’s read from memory. less waiting time for processor, more complex circuitry.</li></ul><li>write miss — info is written directly into main memory</li></ul></div><div><br/></div></body></html>- \ No newline at end of file diff --git a/content/sysarch-notes/Cache memory.md b/content/sysarch-notes/Cache memory.md @@ -0,0 +1,35 @@ ++++ +title = 'Cache memory' ++++ +# Cache memory +very small, very fast + +between processor and main memory, its there to be a wingman and make the main memory look good in front of the processor + +locality of reference — many instructions in localised areas of the program are executed repeatedly during some time period + +- temporal — recently executed is likely to be executed again soon +- spatial — instructions close to a recently executed instruction are likely to be executed again soon + +basically, whenever some info is needed, it should be brought into the cache. and might as well grab data at adjacent addresses too. + +cache block/line — set of contiguous address locations of some size + +the mapping function specifies correspondence between main memory blocks and those in cache + +replacement algorithm decides which blocks to remove to make space for a newly referenced word + +cache hits + +- processor issues read/write requests +- cache control circuitry determines if the requested word is in cache +- if read hit, data is read from cache & main memory is not involved +- if write hit, two options: + - write-through — both cache and main memory are updated + - write-back — update only cache location and mark block with an associated flag bit (dirty/modified bit), main memory is updated later + +cache misses: + +- read miss — the block containing the requested word is copied from main memory into cache, then the word is forwarded to the processor + - load-through — alternative approach where word is sent to processor as soon as it’s read from memory. less waiting time for processor, more complex circuitry. +- write miss — info is written directly into main memory diff --git a/content/sysarch-notes/Conversion between bases.html b/content/sysarch-notes/Conversion between bases.html @@ -1,3 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="-0.378695160150528"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-11-09 6:26:12 PM +0000"/><meta name="latitude" content="52.33343534840424"/><meta name="longitude" content="4.867883035036247"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-11-14 5:25:57 PM +0000"/><title>Conversion between bases</title></head><body><div><span style="font-weight: bold;">If one radix is power of other radix</span></div><ul><li>Start right, take groups of size <i>ratio of powers</i> (e.g. hex to octal — 16 (2⁴) to 8 (2³) — 4 to 3 —convert to binary, group by 3s)</li></ul><div><br/></div><div>Ex: </div><table style="border-collapse: collapse; min-width: 100%;"><colgroup><col style="width: 130px;"/><col style="width: 130px;"/><col style="width: 130px;"/></colgroup><tbody><tr><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>Binary (2¹)</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>grouping (1/3)</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>Octal (2³)</div></td></tr><tr><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>10100101001</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>010 100 101 001</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>2 4 5 1</div></td></tr></tbody></table><div><br/></div><div><span style="font-weight: bold;">If not:</span></div><ul><li>Binary to decimal — multiply &amp; add up powers of 2</li><li>Decimal to binary — identify powers of 2 OR repeatedly divide by 2</li></ul><div><br/></div></body></html>- \ No newline at end of file diff --git a/content/sysarch-notes/Conversion between bases.md b/content/sysarch-notes/Conversion between bases.md @@ -0,0 +1,16 @@ ++++ +title = 'Conversion between bases' ++++ +# Conversion between bases +## If one radix is power of other radix +Start right, take groups of size *ratio of powers* (e.g. hex to octal — 16 (2⁴) to 8 (2³) — 4 to 3 —convert to binary, group by 3s) + +Ex: + +| Binary (2¹) | grouping (1/3) | Octal (2³) | +| --- | --- | --- | +| 10100101001 | 010 100 101 001 | 2 4 5 1 | + +## If not: +- Binary to decimal — multiply & add up powers of 2 +- Decimal to binary — identify powers of 2 OR repeatedly divide by 2 diff --git a/content/sysarch-notes/Counters.html b/content/sysarch-notes/Counters.html @@ -1,3 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="2.578593730926514"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-11-09 3:48:58 PM +0000"/><meta name="latitude" content="52.33300923649106"/><meta name="longitude" content="4.865525547823282"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-11-09 3:52:03 PM +0000"/><title>Counters</title></head><body><div><span style="font-weight: bold;">3-bit counter (asynchronous)</span></div><div>below is a counter made with T flip-flops.</div><div>when T is 1, the value changes with each tick.</div><div>Changing from 0 to 1 to 0 takes 2 ticks. This means that Q₀ has a frequency half of the clock, Q₁ a frequency half of Q₀, etc.</div><div>This means we can make a ripple counter.</div><div><br/></div><div><img src="Counters.resources/screenshot.png" height="213" width="538"/><br/></div><div><br/></div></body></html>- \ No newline at end of file diff --git a/content/sysarch-notes/Counters/index.md b/content/sysarch-notes/Counters/index.md @@ -0,0 +1,13 @@ ++++ +title = 'Counters' ++++ +# Counters +## 3-bit counter (asynchronous) +below is a counter made with T flip-flops. +when T is 1, the value changes with each tick. + +Changing from 0 to 1 to 0 takes 2 ticks. This means that Q₀ has a frequency half of the clock, Q₁ a frequency half of Q₀, etc. + +This means we can make a ripple counter. + +![screenshot.png](screenshot-3.png) diff --git a/content/sysarch-notes/Counters.resources/screenshot.png b/content/sysarch-notes/Counters/screenshot-3.png Binary files differ. diff --git a/content/sysarch-notes/Data dependencies.html b/content/sysarch-notes/Data dependencies.html @@ -1,3 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="-0.2610844969749451"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-12-18 12:26:00 PM +0000"/><meta name="latitude" content="52.37360997359432"/><meta name="longitude" content="4.836342293930081"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-12-18 12:45:19 PM +0000"/><title>Data dependencies</title></head><body><div>instructions:</div><div><font face="Courier New">Add R2, R3, #100</font></div><div><font face="Courier New">Subtract R9, R2, #30</font></div><div><font face="Courier New"><br/></font></div><div><font face="Helvetica Neue">R2 is destination for add, and source for subtract</font></div><div><font face="Helvetica Neue">there is a data dependency between the instructions</font></div><div><font face="Helvetica Neue">subtract has to be stalled, like this:</font></div><div><ol><li><font face="Helvetica Neue">Control circuit recognises data dependency when it decodes subtract instruction (compare source/destination registers)</font></li><li><font style="font-family: &quot;Helvetica Neue&quot;;">Subtract instruction is held in interstage buffer B1 during cycles 3-5</font></li><li><font face="Helvetica Neue"><span style="font-family: &quot;Helvetica Neue&quot;;">Add instruction proceeds, s</span>ignals are set in interstage buffer B2 for implicit NOP (no operation) instruction — creates a ‘bubble’ (clock cycle of idle time)</font></li></ol></div><div><font face="Helvetica Neue"><br/></font></div><div><img src="Data%20dependencies.resources/screenshot_1.png" height="221" width="857"/></div><div><br/></div><div><br/></div><div>the stalls can be alleviated using operand forwarding:</div><div><ul><li>in the above example, value is available at the end of cycle 3</li><li>hardware implementation</li><ul><li>hardware can forward the value from RZ to where it’s needed</li><li>modification of datapath needed (new multiplexer)</li></ul><li>software implementation</li><ul><li>compiler can identify dependencies and insert NOPs</li><li>does not decrease time, increases code size</li><li>but hardware isn’t as complicated</li></ul></ul><div><br/></div></div><div>the result of hardware implementation looks like this:</div><div><br/></div><div><img src="Data%20dependencies.resources/screenshot_2.png" height="226" width="674"/></div><div><br/></div><div>The new datapath, incorporating operand forwarding:</div><div><br/></div><div><img src="Data%20dependencies.resources/screenshot.png" height="882" width="537"/></div><div><br/></div></body></html>- \ No newline at end of file diff --git a/content/sysarch-notes/Data dependencies/index.md b/content/sysarch-notes/Data dependencies/index.md @@ -0,0 +1,40 @@ ++++ +title = 'Data dependencies' ++++ +# Data dependencies +instructions: +- Add R2, R3, #100 +- Subtract R9, R2, #30 + +R2 is destination for add, and source for subtract + +there is a data dependency between the instructions + +subtract has to be stalled, like this: + +1. Control circuit recognises data dependency when it decodes subtract instruction (compare source/destination registers) + +2. Subtract instruction is held in interstage buffer B1 during cycles 3-5 + +3. Add instruction proceeds, signals are set in interstage buffer B2 for implicit NOP (no operation) instruction — creates a ‘bubble’ (clock cycle of idle time) + +![screenshot.png](screenshot-4.png) + +the stalls can be alleviated using operand forwarding: + +- in the above example, value is available at the end of cycle 3 +- hardware implementation + - hardware can forward the value from RZ to where it’s needed + - modification of datapath needed (new multiplexer) +- software implementation + - compiler can identify dependencies and insert NOPs + - does not decrease time, increases code size + - but hardware isn’t as complicated + +the result of hardware implementation looks like this: + +![screenshot.png](screenshot-6.png) + +The new datapath, incorporating operand forwarding: + +![screenshot.png](screenshot-5.png) diff --git a/content/sysarch-notes/Data dependencies.resources/screenshot_1.png b/content/sysarch-notes/Data dependencies/screenshot-4.png Binary files differ. diff --git a/content/sysarch-notes/Data dependencies.resources/screenshot.png b/content/sysarch-notes/Data dependencies/screenshot-5.png Binary files differ. diff --git a/content/sysarch-notes/Data dependencies.resources/screenshot_2.png b/content/sysarch-notes/Data dependencies/screenshot-6.png Binary files differ. diff --git a/content/sysarch-notes/Data path & instructions.html b/content/sysarch-notes/Data path & instructions.html @@ -1,3 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="-0.3448867201805115"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-12-16 10:38:45 PM +0000"/><meta name="latitude" content="52.37359297352734"/><meta name="longitude" content="4.836362365770766"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-12-16 10:39:19 PM +0000"/><title>Data path &amp; instructions</title></head><body><div><span style="font-weight: bold;">Overall data path:</span></div><div>organised in five stages, according to steps executed</div><ol><li>Instruction fetch</li><li>Load from source registers</li><li>ALU computes</li><li>Memory access</li><li>Save to destination register</li></ol><div><br style="font-weight: bold;"/></div><div><img src="Data%20path%20&amp;%20instructions.resources/screenshot_1.png" height="983" width="666"/><br/></div><div><br/></div><div><span style="font-weight: bold;">Instruction fetch section</span></div><div>address for memory access come from PC for instructions, from RZ for operands</div><div>instruction address generator (includes PC) updates contents of PC after fetch</div><div>instruction loaded into IR, examined by control circuitry to generate signals</div><div>immediate values are sign-extended to 32 bits</div><div><br/></div><div><img src="Data%20path%20&amp;%20instructions.resources/screenshot.png" height="469" width="596"/></div><div><br/></div><div><span style="font-weight: bold;">Instruction fetch &amp; execution in steps</span></div><div>with an example instruction: ADD R3, R4, R5</div><div><br/></div><ol><li>Fetch instruction and place in IR</li><li>Contents of R4, R5 move to RA, RB</li><li>Control circuitry sets MuxB to input 0 (RB), causes ALU to add RA+RB into RZ</li><li>MuxY selects input 0, RZ moves to RY. Control circuitry connects destination address to input for port C of register file</li><li>Write RY to R3</li></ol><div><br/></div><div><span style="font-weight: bold;">Waiting for memory</span></div><div>when requested info isn’t in cache and has to be fetched from main memory, multiple clock cycles may be needed</div><div>processor-memory interface circuit generates a Memory Function Completed (MFC) signal</div><div>if the data is in cache, MFC signal is asserted before the end of the clock cycle</div><div><br/></div><div><span style="font-weight: bold;">How are control signals generated?</span></div><div>either hardwired or microprogrammed control</div><div><br/></div><div>hardwired — setting of signals depends on:</div><ul><li>contents of step counter</li><li>contents of instruction register</li><li>results of computation/comparison</li><li>external input signals (e.g. interrupts)</li></ul><div><br/></div><div><br/></div></body></html>- \ No newline at end of file diff --git a/content/sysarch-notes/Data path & instructions/index.md b/content/sysarch-notes/Data path & instructions/index.md @@ -0,0 +1,50 @@ ++++ +title = 'Data path & instructions' ++++ +# Data path & instructions +## Overall data path: +organised in five stages, according to steps executed +1. Instruction fetch +2. Load from source registers +3. ALU computes +4. Memory access +5. Save to destination register + +![screenshot.png](screenshot-9.png) + +## Instruction fetch section +address for memory access come from PC for instructions, from RZ for operands +instruction address generator (includes PC) updates contents of PC after fetch +instruction loaded into IR, examined by control circuitry to generate signals +immediate values are sign-extended to 32 bits + +![screenshot.png](screenshot-8.png) + +## Instruction fetch & execution in steps +with an example instruction: ADD R3, R4, R5 + +1. Fetch instruction and place in IR +2. Contents of R4, R5 move to RA, RB +3. Control circuitry sets MuxB to input 0 (RB), causes ALU to add RA+RB into RZ + +4. MuxY selects input 0, RZ moves to RY. Control circuitry connects destination address to input for port C of register file + +5. Write RY to R3 + +## Waiting for memory + +when requested info isn’t in cache and has to be fetched from main memory, multiple clock cycles may be needed + +processor-memory interface circuit generates a Memory Function Completed (MFC) signal + +if the data is in cache, MFC signal is asserted before the end of the clock cycle + +## How are control signals generated? +either hardwired or microprogrammed control + +hardwired — setting of signals depends on: + +- contents of step counter +- contents of instruction register +- results of computation/comparison +- external input signals (e.g. interrupts) diff --git a/content/sysarch-notes/Data path & instructions.resources/screenshot.png b/content/sysarch-notes/Data path & instructions/screenshot-8.png Binary files differ. diff --git a/content/sysarch-notes/Data path & instructions.resources/screenshot_1.png b/content/sysarch-notes/Data path & instructions/screenshot-9.png Binary files differ. diff --git a/content/sysarch-notes/Decoders.html b/content/sysarch-notes/Decoders.html @@ -1,3 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="-0.2807037234306335"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-11-09 4:58:48 PM +0000"/><meta name="latitude" content="52.33343557965415"/><meta name="longitude" content="4.867981343916237"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-11-09 5:42:24 PM +0000"/><title>Decoders</title></head><body><div>a circuit capable of accepting a n-variable input and generating corresponding signal on one out of 2<span style="vertical-align: super;">n</span> outputs</div><div>select one output based on the inputs, and give it a value of 1</div><div><img src="Decoders.resources/screenshot.png" height="379" width="638"/></div><div><br/></div></body></html>- \ No newline at end of file diff --git a/content/sysarch-notes/Decoders/index.md b/content/sysarch-notes/Decoders/index.md @@ -0,0 +1,9 @@ ++++ +title = 'Decoders' ++++ +# Decoders +a circuit capable of accepting a n-variable input and generating corresponding signal on one out of 2ⁿ outputs + +select one output based on the inputs, and give it a value of 1 + +![screenshot.png](screenshot-33.png) diff --git a/content/sysarch-notes/Decoders.resources/screenshot.png b/content/sysarch-notes/Decoders/screenshot-33.png Binary files differ. diff --git a/content/sysarch-notes/Direct Memory Access (DMA).html b/content/sysarch-notes/Direct Memory Access (DMA).html @@ -1,3 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="-0.3009934425354004"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-12-17 6:30:53 PM +0000"/><meta name="latitude" content="52.37361692187181"/><meta name="longitude" content="4.836262575463552"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-12-17 6:36:01 PM +0000"/><title>Direct Memory Access (DMA)</title></head><body><div>A special control unit to manage the transfer of blocks directly between main memory and devices</div><div>does functions normally carried out by processor when accessing main memory</div><div>its operation is under control of an operating system routine, but transfers data without intervention</div><div><br/></div><div>to transfer a block of words:</div><div><ol><li>Processor sends to DMA controller: starting address, num of words in block, direction of transfer</li><li>DMA controller performs requested operation</li><li>When complete, informs processor by raising an interrupt</li></ol><div><br/></div></div><div><br/></div></body></html>- \ No newline at end of file diff --git a/content/sysarch-notes/Direct Memory Access (DMA).md b/content/sysarch-notes/Direct Memory Access (DMA).md @@ -0,0 +1,15 @@ ++++ +title = 'Direct Memory Access (DMA)' ++++ +# Direct Memory Access (DMA) +A special control unit to manage the transfer of blocks directly between main memory and devices + +does functions normally carried out by processor when accessing main memory + +its operation is under control of an operating system routine, but transfers data without intervention + +to transfer a block of words: + +1. Processor sends to DMA controller: starting address, num of words in block, direction of transfer +2. DMA controller performs requested operation +3. When complete, informs processor by raising an interrupt diff --git a/content/sysarch-notes/Empirical Laws of Computing.html b/content/sysarch-notes/Empirical Laws of Computing.html @@ -1,3 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="-0.07572704553604126"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-10-31 4:44:06 PM +0000"/><meta name="latitude" content="52.33336786659279"/><meta name="longitude" content="4.866345896199826"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-10-31 4:48:06 PM +0000"/><title>Empirical Laws of Computing</title></head><body><div>Moore’s law: density of silicon chip (number of transistors) increases 2x every 1.5 (2) years</div><div>Rock’s law: cost of equipment to produce chips increases 2x every 4 years</div><div>Koomey’s law: energy efficiency increases 2x every 1.5 years</div><div>Metcalfe’s law: usefulness of network ~n<font style="font-size: 14px;"><sup>2</sup> for n users/objects</font></div><div><font style="font-size: 14px;"><br/></font></div></body></html>- \ No newline at end of file diff --git a/content/sysarch-notes/Empirical Laws of Computing.md b/content/sysarch-notes/Empirical Laws of Computing.md @@ -0,0 +1,11 @@ ++++ +title = 'Empirical laws of computing' ++++ +# Empirical laws of computing +Moore’s law: density of silicon chip (number of transistors) increases 2x every 1.5 (2) years + +Rock’s law: cost of equipment to produce chips increases 2x every 4 years + +Koomey’s law: energy efficiency increases 2x every 1.5 years + +Metcalfe’s law: usefulness of network is around n² for n users/objects diff --git a/content/sysarch-notes/Flip-Flops.html b/content/sysarch-notes/Flip-Flops.html @@ -1,3 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="-0.4269982278347015"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-11-09 1:14:25 PM +0000"/><meta name="latitude" content="52.33344899833077"/><meta name="longitude" content="4.868301745244982"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-11-09 6:09:21 PM +0000"/><title>Flip-Flops</title></head><body><div><span style="font-weight: bold;">SR Latch</span><br/></div><div>Circuit of two NOR gates that can ‘remember’ which input was most recently 1 (in this case, R).</div><div>The state R = S = 0 is undefined, the state R = S = 1 is unused.</div><div><br/></div><div><img src="Flip-Flops.resources/screenshot_4.png" height="166" width="440"/><br/></div><div><br/></div><div><span style="font-weight: bold;">Gated SR Latch</span></div><div>When the time at which to set or reset is controlled by a clock instead of the inputs</div><div>When the clock is at 1, signals R’ and S’ change based on R and S.</div><div>When the clock is at 0, no change in the state can happen.</div><div><br/></div><div>Implementation with NAND gates? Just replace every gate with a NAND. It works. Trust me, I’m a computer scientist.</div><div><br/></div><div><img src="Flip-Flops.resources/screenshot_3.png" height="186" width="613"/><br/></div><div><br/></div><div><span style="font-weight: bold;">Gated D latch</span></div><div>Instead of using two separate inputs, you can derive the inputs from one input, D (data):</div><div><br/></div><div><img src="Flip-Flops.resources/screenshot_1.png" height="201" width="608"/><br/></div><div><br/></div><div><span style="font-weight: bold;">T flip-flop</span></div><div>changes state every clock cycle if its input T is 1 — “toggles state”</div><div><br/></div><div><img src="Flip-Flops.resources/screenshot_2.png" height="277" width="554"/><br/></div><div><br/></div><div><span style="font-weight: bold;">Master-slave flip-flop</span></div><div>What if you don’t want a change in the input to be immediately propagated to the output?</div><div>Connect two gated D latches to create a master-slave flip-flop.</div><div>While clock is 1, master is affected by changes in D but slave stays in the same state.</div><div>When clock changes from 1 to 0, output is propagated to the slave.</div><div><img src="Flip-Flops.resources/screenshot.png" height="297" width="583"/><br/></div><div><br/></div></body></html>- \ No newline at end of file diff --git a/content/sysarch-notes/Flip-Flops/index.md b/content/sysarch-notes/Flip-Flops/index.md @@ -0,0 +1,45 @@ ++++ +title = 'Flip-flops' ++++ +# Flip-flops +## SR Latch + +Circuit of two NOR gates that can ‘remember’ which input was most recently 1 (in this case, R). + +The state R = S = 0 is undefined, the state R = S = 1 is unused. + +![screenshot.png](screenshot-45.png) + +## Gated SR Latch + +When the time at which to set or reset is controlled by a clock instead of the inputs + +When the clock is at 1, signals R’ and S’ change based on R and S. +When the clock is at 0, no change in the state can happen. + +Implementation with NAND gates? Just replace every gate with a NAND. It works. Trust me, I’m a computer scientist. + +![screenshot.png](screenshot-46.png) + +## Gated D latch + +Instead of using two separate inputs, you can derive the inputs from one input, D (data): + +![screenshot.png](screenshot-47.png) + +## T flip-flop +changes state every clock cycle if its input T is 1 — "toggles state" + +![screenshot.png](screenshot-43.png) + +## Master-slave flip-flop + +What if you don’t want a change in the input to be immediately propagated to the output? + +Connect two gated D latches to create a master-slave flip-flop. + +While clock is 1, master is affected by changes in D but slave stays in the same state. + +When clock changes from 1 to 0, output is propagated to the slave. + +![screenshot.png](screenshot-44.png) diff --git a/content/sysarch-notes/Flip-Flops.resources/screenshot_2.png b/content/sysarch-notes/Flip-Flops/screenshot-43.png Binary files differ. diff --git a/content/sysarch-notes/Flip-Flops.resources/screenshot.png b/content/sysarch-notes/Flip-Flops/screenshot-44.png Binary files differ. diff --git a/content/sysarch-notes/Flip-Flops.resources/screenshot_4.png b/content/sysarch-notes/Flip-Flops/screenshot-45.png Binary files differ. diff --git a/content/sysarch-notes/Flip-Flops.resources/screenshot_3.png b/content/sysarch-notes/Flip-Flops/screenshot-46.png Binary files differ. diff --git a/content/sysarch-notes/Flip-Flops.resources/screenshot_1.png b/content/sysarch-notes/Flip-Flops/screenshot-47.png Binary files differ. diff --git a/content/sysarch-notes/Hardware components.html b/content/sysarch-notes/Hardware components.html @@ -1,3 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="-0.3722517490386963"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-12-14 3:50:52 PM +0000"/><meta name="latitude" content="52.3330098593966"/><meta name="longitude" content="4.865517190619684"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-12-16 10:58:33 PM +0000"/><title>Hardware components</title></head><body><div><b>Von Neumann Architecture</b></div><div><img src="Hardware%20components.resources/1200px-Von_Neumann_Architecture.svg.png" height="694" width="1200"/></div><div><br/></div><div><b>Organisation of the Central Processing Unit (CPU)</b></div><div><b><br/></b></div><div><img src="Hardware%20components.resources/CPU.png" height="571" width="691"/></div><div><b><br/></b></div><div><span style="font-weight: bold;">Register file</span></div><div>small and fast memory block, array of storage elements</div><div>circuitry that enables data to be read from or written to any register</div><div>access circuitry:</div><div><ul><li>read</li><ul><li>enables two registers to be read at the same time</li><li>has two address inputs to select registers to be read</li><li>dual-ported: contents of two registers is available via two separate outputs A and B (ports)</li></ul><li>write</li><ul><li>data input C and corresponding address input for read</li></ul></ul><div><br/></div></div><div>how to realise dual-ported memory units:</div><div><br/></div><div><div><br/></div><table style="border-collapse: collapse; min-width: 100%;"><colgroup><col style="width: 298px;"/><col style="width: 340px;"/></colgroup><tbody><tr><td style="border: 1px solid rgb(255, 255, 255); width: 298px; padding: 8px;"><div>Single memory block</div></td><td style="border: 1px solid rgb(255, 255, 255); width: 340px; padding: 8px;"><div>Two memory blocks</div></td></tr><tr><td style="border: 1px solid rgb(255, 255, 255); width: 298px; padding: 8px;"><div><img src="Hardware%20components.resources/screenshot.png" height="346" width="332"/><br/></div></td><td style="border: 1px solid rgb(255, 255, 255); width: 340px; padding: 8px;"><div><img src="Hardware%20components.resources/screenshot_2.png" height="341" width="415"/><br/></div></td></tr></tbody></table><div><br/></div></div><div><span style="font-weight: bold;">ALU</span></div><div>used to manipulate data, performs add/subtract and logic (AND, OR, XOR)</div><div>two inputs — one from register out A, one from multiplexer</div><div>multiplexer either selects register out B, or immediate value in IR</div><div>output is connected to data input of registers</div><div><br/></div><div><img src="Hardware%20components.resources/screenshot_1.png" height="591" width="484"/><br/></div><div><br/></div><div><br/></div></body></html>- \ No newline at end of file diff --git a/content/sysarch-notes/Hardware components.resources/1200px-Von_Neumann_Architecture.svg.png b/content/sysarch-notes/Hardware components/1200px-Von_Neumann_Architecture.svg.png Binary files differ. diff --git a/content/sysarch-notes/Hardware components.resources/CPU.png b/content/sysarch-notes/Hardware components/CPU.png Binary files differ. diff --git a/content/sysarch-notes/Hardware components/index.md b/content/sysarch-notes/Hardware components/index.md @@ -0,0 +1,43 @@ ++++ +title = 'Hardware components' ++++ +# Hardware components +## Von Neumann Architecture + +![1200px-Von_Neumann_Architecture.svg.png](1200px-Von_Neumann_Architecture.svg.png) + +## Organisation of the Central Processing Unit (CPU) + +![CPU.png](CPU.png) + + +## Register file +small and fast memory block, array of storage elements + +circuitry that enables data to be read from or written to any register + +access circuitry: + +- read + - enables two registers to be read at the same time + - has two address inputs to select registers to be read + - dual-ported: contents of two registers is available via two separate outputs A and B (ports) +- write + - data input C and corresponding address input for read + +how to realise dual-ported memory units: + +| Single memory block | Two memory blocks | +| --- | --- | +| ![screenshot.png](screenshot-59.png) | ![screenshot.png](screenshot-61.png) | + +## ALU +used to manipulate data, performs add/subtract and logic (AND, OR, XOR) + +two inputs — one from register out A, one from multiplexer + +multiplexer either selects register out B, or immediate value in IR + +output is connected to data input of registers + +![screenshot.png](screenshot-60.png) diff --git a/content/sysarch-notes/Hardware components.resources/screenshot.png b/content/sysarch-notes/Hardware components/screenshot-59.png Binary files differ. diff --git a/content/sysarch-notes/Hardware components.resources/screenshot_1.png b/content/sysarch-notes/Hardware components/screenshot-60.png Binary files differ. diff --git a/content/sysarch-notes/Hardware components.resources/screenshot_2.png b/content/sysarch-notes/Hardware components/screenshot-61.png Binary files differ. diff --git a/content/sysarch-notes/Instruction Set Architecture.html b/content/sysarch-notes/Instruction Set Architecture.html @@ -1,3 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="1.336796760559082"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-11-21 2:55:27 PM +0000"/><meta name="latitude" content="52.33300174513328"/><meta name="longitude" content="4.865523109236122"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-11-21 4:17:32 PM +0000"/><title>Instruction Set Architecture</title></head><body><div>How to program a computer:</div><div><ol><li>Create model for programmable digital computer</li><li>Specify programming interface for each computer</li><li>Specify a generic programming language that works for all computers (software)</li><li>Design digital computers that match specific/general interface (hardware)</li><li>Design software engineering techniques to simplify and optimise coding (software stack)</li></ol><div><br/></div></div><div>A platform (simplified) is a set of technologies common to many applications.</div><div>ISA: list of instructions a computer can perform, grouped by type</div><div><br/></div><div>Von Neumann Architecture — memory connects to CPU. CPU receives input and sends output.</div><div>CPU contains registers, arithmetic and logic unit, control unit.</div><div><br/></div><div>How to compare ISA:</div><div><ol><li>Complexity of what the ISA can do (flexibility)</li><li>Complexity for programmer (programmability)</li><li>Complexity for the hardware (implementation cost)</li></ol><div><br/></div></div><div>Memory structure:</div><div><ul><li>1 byte is 8 bits</li><li>1 word is 32 bits (4 bytes)<input type="checkbox"/></li></ul></div><div><br/></div></body></html>- \ No newline at end of file diff --git a/content/sysarch-notes/Instruction Set Architecture.md b/content/sysarch-notes/Instruction Set Architecture.md @@ -0,0 +1,29 @@ ++++ +title = 'Instruction Set Architecture' ++++ +How to program a computer: +1. Create model for programmable digital computer +2. Specify programming interface for each computer + +3. Specify a generic programming language that works for all computers (software) + +4. Design digital computers that match specific/general interface (hardware) + +5. Design software engineering techniques to simplify and optimise coding (software stack) + +A platform (simplified) is a set of technologies common to many applications. +ISA: list of instructions a computer can perform, grouped by type + +Von Neumann Architecture — memory connects to CPU. CPU receives input and sends output. + +CPU contains registers, arithmetic and logic unit, control unit. + +How to compare ISA: +1. Complexity of what the ISA can do (flexibility) +2. Complexity for programmer (programmability) +3. Complexity for the hardware (implementation cost) + +Memory structure: + +- 1 byte is 8 bits +- 1 word is 32 bits (4 bytes)- [ ] diff --git a/content/sysarch-notes/Instruction execution.html b/content/sysarch-notes/Instruction execution.html @@ -1,3 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="-0.4324055016040802"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-12-14 3:34:00 PM +0000"/><meta name="latitude" content="52.33300107849124"/><meta name="longitude" content="4.865514777109206"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-12-16 9:52:37 PM +0000"/><title>Instruction execution</title></head><body><div>LOAD (e.g. Load R5, X(R7))</div><div><ol><li>Fetch instruction, increment PC</li><li>Decode instruction, read contents of R7</li><li>Compute effective address</li><li>Read memory source operand</li><li>Load operand into destination R5</li></ol><div><br/></div><div>STORE (e.g. Store R6, X(R8))</div><div><ol><li>Fetch instruction, increment PC</li><li>Decode instruction, read R6 and R8</li><li>Compute effective address of X+[R8]</li><li>Store contents of R6 into memory location X+[R8]</li><li>No action</li></ol></div><div><br/></div><div>Arithmetic &amp; Logic (e.g. Add R3, R4, R5)</div><div><ol><li>Fetch instruction, increment PC</li><li>Decode instruction, read contents of R4, R5</li><li>Compute sum [R4] + [R5]</li><li>No action</li><li>Load result into destination R3</li></ol><div><br/></div></div></div><div><br/></div></body></html>- \ No newline at end of file diff --git a/content/sysarch-notes/Instruction execution.md b/content/sysarch-notes/Instruction execution.md @@ -0,0 +1,24 @@ ++++ +title = 'Instruction execution' ++++ +# Instruction execution +LOAD (e.g. Load R5, X(R7)) +1. Fetch instruction, increment PC +2. Decode instruction, read contents of R7 +3. Compute effective address +4. Read memory source operand +5. Load operand into destination R5 + +STORE (e.g. Store R6, X(R8)) +1. Fetch instruction, increment PC +2. Decode instruction, read R6 and R8 +3. Compute effective address of X+[R8] +4. Store contents of R6 into memory location X+[R8] +5. No action + +Arithmetic & Logic (e.g. Add R3, R4, R5) +1. Fetch instruction, increment PC +2. Decode instruction, read contents of R4, R5 +3. Compute sum [R4] + [R5] +4. No action +5. Load result into destination R3 diff --git a/content/sysarch-notes/Internal organisation of memory chips.html b/content/sysarch-notes/Internal organisation of memory chips.html @@ -1,3 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="-0.3010561764240265"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-12-17 5:15:37 PM +0000"/><meta name="latitude" content="52.37362890561555"/><meta name="longitude" content="4.836362144176305"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-12-17 5:28:39 PM +0000"/><title>Internal organisation of memory chips</title></head><body><div>organised in form of array, one cell stores one bit of info</div><div>each row constitutes a memory word, all cells of a row are connected to a common line (‘word line’)</div><div>each column is connected to a Sense/Write circuit by two bit lines</div><div><br/></div><div>an example of 16 x 8 organisation (16 words, 8 bits each):</div><div><br/></div><div><br/></div><div><img src="Internal%20organisation%20of%20memory%20chips.resources/screenshot.png" height="539" width="765"/></div><div><br/></div><div><br/></div><div>a second way of organising is, for example, a 1024 memory cell circuit organised in a 1K x 1 format (1000 words, 1 bit each):</div><div><br/></div><div><img src="Internal%20organisation%20of%20memory%20chips.resources/screenshot_1.png" height="491" width="726"/></div><div><br/></div></body></html>- \ No newline at end of file diff --git a/content/sysarch-notes/Internal organisation of memory chips/index.md b/content/sysarch-notes/Internal organisation of memory chips/index.md @@ -0,0 +1,17 @@ ++++ +title = 'Internal organisation of memory chips' ++++ +# Internal organisation of memory chips +organised in form of array, one cell stores one bit of info + +each row constitutes a memory word, all cells of a row are connected to a common line (‘word line’) + +each column is connected to a Sense/Write circuit by two bit lines + +an example of 16 x 8 organisation (16 words, 8 bits each): + +![screenshot.png](screenshot-37.png) + +a second way of organising is, for example, a 1024 memory cell circuit organised in a 1K x 1 format (1000 words, 1 bit each): + +![screenshot.png](screenshot-36.png) diff --git a/content/sysarch-notes/Internal organisation of memory chips.resources/screenshot_1.png b/content/sysarch-notes/Internal organisation of memory chips/screenshot-36.png Binary files differ. diff --git a/content/sysarch-notes/Internal organisation of memory chips.resources/screenshot.png b/content/sysarch-notes/Internal organisation of memory chips/screenshot-37.png Binary files differ. diff --git a/content/sysarch-notes/Interrupts.html b/content/sysarch-notes/Interrupts.html @@ -1,3 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="0.01143651083111763"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-12-17 12:46:30 PM +0000"/><meta name="latitude" content="52.37355020663739"/><meta name="longitude" content="4.83620649643994"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-12-17 1:33:02 PM +0000"/><title>Interrupts</title></head><body><div>if the program was just waiting for a signal from an I/O device it would be an insane waste of time. that’s why they invented interrupts.</div><div>interrupt request — hardware signal sent by I/O device</div><div>after a processor receives this signal, it responds through an interrupt-service routine</div><div>after interrupt-service routine is done, an interrupt acknowledge signal is sent to the device</div><div>interrupts can be enabled/disabled by setting the IE bit of the status register PS</div><div><br/></div><div>btw, also used in exceptions and debugging!</div><div><br/></div><div>Example execution:</div><div><ol><li>Device raises an interrupt request, interrupt request arrives during execution of instruction <i>i</i></li><li>Processor completes execution of instruction <i>i</i></li><li>Saves contents of PC (counter) and PS (status)</li><li>Interrupts are disabled by setting IE bit of PS to 0</li><li>Processor loads PC with address of first instruction of interrupt-service routine, routine is executed</li><li>After execution, PC and PS are restored (including setting IE bit to 1)</li><li>Processor continues from instruction <i>i</i>+1</li></ol><div><br/></div></div><div><img src="Interrupts.resources/screenshot.png" height="425" width="816"/></div><div><br/></div><div><b>Multiple devices</b></div><div>organised in a priority structure</div><div>priority level of processor is priority of program that is being executed</div><div>only interrupts from higher priorities than the processor's are accepted</div><div><b><br/></b></div><div>option 1 — polling</div><div><ul><li>poll all devices</li><li>the first to set the IRQ bit of PS to 1 is serviced<br/></li></ul></div><div><br/></div><div>option 2 — vectored interrupts</div><div><ul><li>allocate area in memory to hold addresses of interrupt-service routines (interrupt vectors)</li><li>each device identifies itself on request</li><li>the info provided by requesting device is a pointer into the interrupt-vector table</li></ul><div><br/></div></div><div><br/></div><div><br/></div></body></html>- \ No newline at end of file diff --git a/content/sysarch-notes/Interrupts/index.md b/content/sysarch-notes/Interrupts/index.md @@ -0,0 +1,48 @@ ++++ +title = 'Interrupts' ++++ +# Interrupts +if the program was just waiting for a signal from an I/O device it would be an insane waste of time. that’s why they invented interrupts. + +interrupt request — hardware signal sent by I/O device + +after a processor receives this signal, it responds through an interrupt-service routine + +after interrupt-service routine is done, an interrupt acknowledge signal is sent to the device + +interrupts can be enabled/disabled by setting the IE bit of the status register PS + +btw, also used in exceptions and debugging! + +Example execution: + +1. Device raises an interrupt request, interrupt request arrives during execution of instruction *i* + +2. Processor completes execution of instruction *i* +3. Saves contents of PC (counter) and PS (status) +4. Interrupts are disabled by setting IE bit of PS to 0 + +5. Processor loads PC with address of first instruction of interrupt-service routine, routine is executed + +6. After execution, PC and PS are restored (including setting IE bit to 1) +7. Processor continues from instruction *i*+1 + +![screenshot.png](screenshot-32.png) + +## Multiple devices +organised in a priority structure + +priority level of processor is priority of program that is being executed + +only interrupts from higher priorities than the processor's are accepted + +option 1 — polling + +- poll all devices +- the first to set the IRQ bit of PS to 1 is serviced + +option 2 — vectored interrupts + +- allocate area in memory to hold addresses of interrupt-service routines (interrupt vectors) +- each device identifies itself on request +- the info provided by requesting device is a pointer into the interrupt-vector table diff --git a/content/sysarch-notes/Interrupts.resources/screenshot.png b/content/sysarch-notes/Interrupts/screenshot-32.png Binary files differ. diff --git a/content/sysarch-notes/Karnaugh Maps.html b/content/sysarch-notes/Karnaugh Maps.html @@ -1,3 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="-4.241825557471657e-09"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-11-08 2:34:46 PM +0000"/><meta name="latitude" content="52.33308902708033"/><meta name="longitude" content="4.866490141020141"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-11-09 12:03:36 AM +0000"/><title>Karnaugh Maps</title></head><body><div><span style="font-weight: bold;">Given a truth table:</span></div><table style="border-collapse: collapse; min-width: 100%;"><colgroup><col style="width: 130px;"/><col style="width: 130px;"/><col style="width: 130px;"/><col style="width: 130px;"/><col style="width: 130px;"/></colgroup><tbody><tr><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div><br/></div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div><span style="font-weight: bold;">x₁</span></div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div><span style="font-weight: bold;">x₂</span></div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div><span style="font-weight: bold;">x₃</span></div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div><span style="font-weight: bold;">ƒ₁</span></div></td></tr><tr><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>m₁</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>0</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>0</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div><span style="background-color: rgb(255, 255, 255);">0</span></div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div><span style="background-color: rgb(255, 255, 255);">1</span></div></td></tr><tr><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>m₂</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>0</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>0</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>1</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>1</div></td></tr><tr><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>m₃</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>0</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>1</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>0</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>0</div></td></tr><tr><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>m₄</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>0</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>1</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>1</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>1</div></td></tr><tr><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>m₅</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>1</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>0</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>0</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>0</div></td></tr><tr><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>m₆</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>1</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>0</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>1</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>0</div></td></tr><tr><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>m₇</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>1</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>1</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>0</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>0</div></td></tr><tr><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>m₈</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>1</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>1</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>1</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>1</div></td></tr></tbody></table><div><span style="font-weight: bold;">Make a table such as this:</span></div><div>Adjacent cells can only differ in one bit!</div><div><div><br/></div><table style="border-collapse: collapse; min-width: 100%;"><colgroup><col style="width: 107px;"/><col style="width: 130px;"/><col style="width: 130px;"/><col style="width: 130px;"/><col style="width: 130px;"/></colgroup><tbody><tr><td style="border: 1px solid rgb(219, 219, 219); width: 107px; padding: 8px;"><div>A/BC    </div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>00</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>01</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>11</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>10</div></td></tr><tr><td style="border: 1px solid rgb(219, 219, 219); width: 107px; padding: 8px;"><div>0</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>m₁: 1</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>m₂: 1</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>m₄: 1</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>m₃: 0</div></td></tr><tr><td style="border: 1px solid rgb(219, 219, 219); width: 107px; padding: 8px;"><div>1</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>m₅: 0</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>m₆: 0</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>m₇: 0</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>m₈: 1</div></td></tr></tbody></table><div><br/></div></div><div>Then choose groups of 1s of size 2<span style="vertical-align: super;">n</span>. They should be as big as possible. Then you see what changes within the groups, and if a bit changes to its complement so that it cancels out to 1, you don’t have to include it.</div></body></html>- \ No newline at end of file diff --git a/content/sysarch-notes/Karnaugh Maps.md b/content/sysarch-notes/Karnaugh Maps.md @@ -0,0 +1,26 @@ ++++ +title = 'Karnaugh maps' ++++ +# Karnaugh maps +## Given a truth table: + +| | x₁ | x₂ | x₃ | ƒ₁ | +| --- | --- | --- | --- | --- | +| m₁ | 0 | 0 | 0 | 1 | +| m₂ | 0 | 0 | 1 | 1 | +| m₃ | 0 | 1 | 0 | 0 | +| m₄ | 0 | 1 | 1 | 1 | +| m₅ | 1 | 0 | 0 | 0 | +| m₆ | 1 | 0 | 1 | 0 | +| m₇ | 1 | 1 | 0 | 0 | +| m₈ | 1 | 1 | 1 | 1 | + +## Make a table such as this: +Adjacent cells can only differ in one bit! + +| A/BC | 00 | 01 | 11 | 10 | +| --- | --- | --- | --- | --- | +| 0 | m₁: 1 | m₂: 1 | m₄: 1 | m₃: 0 | +| 1 | m₅: 0 | m₆: 0 | m₇: 0 | m₈: 1 | + +Then choose groups of 1s of size 2ⁿ. They should be as big as possible. Then you see what changes within the groups, and if a bit changes to its complement so that it cancels out to 1, you don’t have to include it. diff --git a/content/sysarch-notes/Mapping functions.html b/content/sysarch-notes/Mapping functions.html @@ -1,3 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="0.006018927320837975"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-12-17 7:24:46 PM +0000"/><meta name="latitude" content="52.37352693909417"/><meta name="longitude" content="4.836185782601543"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-12-17 8:44:26 PM +0000"/><title>Mapping functions</title></head><body><div>consider (with 16-bit addressable memory):</div><div>cache — 128 blocks of 16 words each = 2048 words (2K)</div><div>main memory — 4096 blocks of 16 words each = 64K words</div><div>valid bit — 0 when power first turned on. set to 1 when a memory block is loaded into a location. the processor only fetches data from a cache block if the valid bit is 1.</div><div>cache flushing — forcing all dirty blocks to be written back to memory</div><div><br/></div><div>Direct mapping:</div><div><ul><li>block <span style="font-style: italic;">j</span> of main memory is block <span style="font-style: italic;">j</span> modulo 128 of cache</li><ul><li>e.g. block 0, 128, 256… of memory is stored in cache block 0</li><li>e.g. block 1, 129, 257… of memory is stored in cache block 1</li><li>etc.</li></ul><li>replacement algorithm is trivial — placement of block is determined by its memory address (three fields tag, block, word)</li></ul><div><br/></div></div><div>Associative mapping:</div><div><ul><li>a main memory block can be placed into any cache block position</li><li>12 tag bits identify a memory block in the cache</li><li>new block replaces an existing block only if cache is full</li><li>more efficient use of space, but higher complexity because of need for parallel tag search (associative search)</li></ul><div><br/></div></div><div>Set-associative mapping</div><div><ul><li>blocks of cache are grouped into sets, mapping allows block of main memory to be in any block of a specific set</li><li>gets rid of problem of contention because of a few choices for block placement</li><li>hardware cost reduced because smaller associative search</li></ul><div><br/></div></div><div><b>Replacement algorithms</b></div><div>LRU replacement algorithm</div><div><ul><li>overwrite least recently used block (the one that’s gone the longest without being referenced)</li><li>cache controller must track references to all blocks</li><li><br/></li></ul><div><br/></div></div><div>Random algorithm — quite effective in practice</div><div><br/></div><div><br/></div></body></html>- \ No newline at end of file diff --git a/content/sysarch-notes/Mapping functions.md b/content/sysarch-notes/Mapping functions.md @@ -0,0 +1,40 @@ ++++ +title = 'Mapping functions' ++++ +# Mapping functions +consider (with 16-bit addressable memory): +cache — 128 blocks of 16 words each = 2048 words (2K) +main memory — 4096 blocks of 16 words each = 64K words + +valid bit — 0 when power first turned on. set to 1 when a memory block is loaded into a location. the processor only fetches data from a cache block if the valid bit is 1. + +cache flushing — forcing all dirty blocks to be written back to memory + +Direct mapping: + +- block *j* of main memory is block *j* modulo 128 of cache + - e.g. block 0, 128, 256… of memory is stored in cache block 0 + - e.g. block 1, 129, 257… of memory is stored in cache block 1 + - etc. +- replacement algorithm is trivial — placement of block is determined by its memory address (three fields tag, block, word) + +Associative mapping: + +- a main memory block can be placed into any cache block position +- 12 tag bits identify a memory block in the cache +- new block replaces an existing block only if cache is full +- more efficient use of space, but higher complexity because of need for parallel tag search (associative search) + +Set-associative mapping + +- blocks of cache are grouped into sets, mapping allows block of main memory to be in any block of a specific set +- gets rid of problem of contention because of a few choices for block placement +- hardware cost reduced because smaller associative search + +## Replacement algorithms +LRU replacement algorithm + +- overwrite least recently used block (the one that’s gone the longest without being referenced) +- cache controller must track references to all blocks + +Random algorithm — quite effective in practice diff --git a/content/sysarch-notes/Memory Hierarchy.html b/content/sysarch-notes/Memory Hierarchy.html @@ -1,3 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="-0.3490290641784668"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-12-17 6:36:20 PM +0000"/><meta name="latitude" content="52.37364222894153"/><meta name="longitude" content="4.836288522954751"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-12-17 6:38:33 PM +0000"/><title>Memory Hierarchy</title></head><body><div>static RAM is fast, but larger cells with higher power consumption</div><div>DRAM is reasonable cost, but affordable size is still too small</div><div>Disks are reasonable cost, but much slower</div><div><br/></div><div>therefore, combine!</div><div><br/></div><div>memory hierarchy:</div><div><br/></div><div><img src="Memory%20Hierarchy.resources/screenshot.png" height="573" width="547"/></div><div><br/></div><div><br/></div></body></html>- \ No newline at end of file diff --git a/content/sysarch-notes/Memory delays.html b/content/sysarch-notes/Memory delays.html @@ -1,3 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="-0.1190103739500046"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-12-18 12:47:19 PM +0000"/><meta name="latitude" content="52.37356323888035"/><meta name="longitude" content="4.836278947153073"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-12-18 12:58:42 PM +0000"/><title>Memory delays</title></head><body><div>another cause of pipeline stalls is a delay from memory access</div><div>for example, because of a cache miss</div><div><br/></div><div>instructions:</div><div><font face="Courier New">Load R2, (R3)</font></div><div><font face="Courier New">Subtract R9, R2, #30</font></div><div><font face="Courier New"><br/></font></div><div><font face="Helvetica Neue">even if data for load is found in cache, operand forwarding can’t be done the same way — data read from cache are not available until they are in RY at start of cycle 5</font></div><div><font face="Helvetica Neue">subtract must be stalled for one cycle to delay ALU operation</font></div><div><font face="Helvetica Neue"><br/></font></div><div><img src="Memory%20delays.resources/screenshot.png" height="225" width="726"/></div><div><br/></div><div>eliminating the one-cycle stall:</div><div><div><ul><li>compiler inserts a useful instruction between load and memory-dependent instruction</li><li>otherwise, hardware stalls automatically (or compiler inserts NOP)</li></ul></div><ul/></div><div><br/></div></body></html>- \ No newline at end of file diff --git a/content/sysarch-notes/Memory delays/index.md b/content/sysarch-notes/Memory delays/index.md @@ -0,0 +1,22 @@ ++++ +title = 'Memory delays' ++++ +# Memory delays +another cause of pipeline stalls is a delay from memory access + +for example, because of a cache miss + +instructions: +- Load R2, (R3) +- Subtract R9, R2, #30 + +even if data for load is found in cache, operand forwarding can’t be done the same way — data read from cache are not available until they are in RY at start of cycle 5 + +subtract must be stalled for one cycle to delay ALU operation + +![screenshot.png](screenshot-38.png) + +eliminating the one-cycle stall: + +- compiler inserts a useful instruction between load and memory-dependent instruction +- otherwise, hardware stalls automatically (or compiler inserts NOP) diff --git a/content/sysarch-notes/Memory delays.resources/screenshot.png b/content/sysarch-notes/Memory delays/screenshot-38.png Binary files differ. diff --git a/content/sysarch-notes/Memory hierarchy/index.md b/content/sysarch-notes/Memory hierarchy/index.md @@ -0,0 +1,15 @@ ++++ +title = 'Memory hierarchy' ++++ +# Memory hierarchy +static RAM is fast, but larger cells with higher power consumption + +DRAM is reasonable cost, but affordable size is still too small + +Disks are reasonable cost, but much slower + +therefore, combine! + +memory hierarchy: + +![screenshot.png](screenshot.png) diff --git a/content/sysarch-notes/Memory Hierarchy.resources/screenshot.png b/content/sysarch-notes/Memory hierarchy/screenshot.png Binary files differ. diff --git a/content/sysarch-notes/Memory locations & addresses.html b/content/sysarch-notes/Memory locations & addresses.html @@ -1,3 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="-1.431357145309448"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-12-11 11:08:37 AM +0000"/><meta name="latitude" content="52.333249125602"/><meta name="longitude" content="4.866755076539879"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-12-11 6:06:51 PM +0000"/><title>Memory locations &amp; addresses</title></head><body><div>memory has storage cells, each for one bit</div><div>bits are handled in groups — words</div><div>modern word length — 32 or 64 bits</div><div>32-bit can store four ASCII characters or 32-bit signed number in one word (4 bytes)</div><div><br/></div><div>to retrieve a single item of info, an address is used</div><div>successive addresses refer to successive byte locations in memory (byte-addressable memory)</div><div>in a 32-bit processor, words are located at addresses {0, 4, 8, …}</div><div><br/></div><div>two ways of assignment across words:</div><div><ul><li>big-endian: lower byte addresses are used for more significant (leftmost) bytes of the word (the end bit has the biggest address)</li><li>little-endian: lower byte addresses are used for less significant bytes (the end bit has the lowest address)</li></ul><div><br/></div></div><div>alignment — if words begin at byte addresses that are a multiple of the byte length of a word</div><div><br/></div><div><br/></div><div><br/></div></body></html>- \ No newline at end of file diff --git a/content/sysarch-notes/Memory locations & addresses.md b/content/sysarch-notes/Memory locations & addresses.md @@ -0,0 +1,24 @@ ++++ +title = 'Memory locations & addresses' ++++ +# Memory locations & addresses +memory has storage cells, each for one bit + +bits are handled in groups — words + +modern word length — 32 or 64 bits + +32-bit can store four ASCII characters or 32-bit signed number in one word (4 bytes) + +to retrieve a single item of info, an address is used + +successive addresses refer to successive byte locations in memory (byte-addressable memory) + +in a 32-bit processor, words are located at addresses {0, 4, 8, …} + +two ways of assignment across words: + +- big-endian: lower byte addresses are used for more significant (leftmost) bytes of the word (the end bit has the biggest address) +- little-endian: lower byte addresses are used for less significant bytes (the end bit has the lowest address) + +alignment — if words begin at byte addresses that are a multiple of the byte length of a word diff --git a/content/sysarch-notes/Memory operations & instructions.html b/content/sysarch-notes/Memory operations & instructions.html @@ -1,3 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="-0.2982466220855713"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-12-11 6:07:47 PM +0000"/><meta name="latitude" content="52.3736534682663"/><meta name="longitude" content="4.836205585752691"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-12-11 10:49:57 PM +0000"/><title>Memory operations &amp; instructions</title></head><body><div><span style="font-weight: bold;">Memory operations</span></div><div>to execute an instruction, processor control circuits have to cause word/words containing instruction to be transferred from memory to processor (with operands and results)</div><div>basic operations</div><div><ul><li>read — transfers copy of contents of memory location to processor</li><li>write — transfers item of info from processor to a memory location</li></ul><div><br/></div></div><div><br/></div><div><span style="font-weight: bold;">RISC vs CISC instruction sets</span></div><div>(most processors have a compromise)</div><div><br/></div><div>RISC (Reduced Instruction Set Computers)</div><div><ul><li>simple addressing modes</li><li>each instruction fits in one word</li><li>fewer instructions in set</li><li>arithmetic/logic only on operands in processor registers</li><li>load/store architecture: no direct transfer between memory locations, must be through processor register</li><li>programs tend to be larger in size (more, simpler instructions)</li><ul/></ul></div><div><br/></div><div>CISC (Complex Instruction Set Computers)</div><div><ul><li>more complex addressing modes, e.g.:<br/></li><ul><li>autoincrement— access operand through effective address in passed register, then increment contents of said register</li><li>autodecrement — contents of passed register are decremented and then used as effective address fo operand</li><li>relative — effective address is determined using index mode with PC instead of register</li></ul><li>instructions don’t have to fit into a single word</li><li>more complex instructions</li><li>arithmetic/logic also on both memory locations and registers</li><li>not constrained to load/store architecture</li><ul/></ul></div><div><br/></div><div><span style="font-weight: bold;">Instruction Execution</span></div><div>the processor has a program counter (PC) register, holds address of next instruction</div><div>processor circuits use info in PC to fetch and execute instructions in order of increasing address (straight-line sequencing)</div><div><br/></div><div>executing an instruction</div><div><ol><li>Instruction fetch — instruction fetched from mem location stored in PC and put in instruction register</li><li>Instruction execute — instruction is examined and the operation is performed, PC is incremented by 4.</li></ol><div><br/></div></div><div>branch instructions load new address into PC, allow conditional jumping (jump if greater/less than)</div><div><br/></div><div><br/></div></body></html>- \ No newline at end of file diff --git a/content/sysarch-notes/Memory operations & instructions.md b/content/sysarch-notes/Memory operations & instructions.md @@ -0,0 +1,49 @@ ++++ +title = 'Memory operations & instructions' ++++ +# Memory operations & instructions +## Memory operations + +to execute an instruction, processor control circuits have to cause word/words containing instruction to be transferred from memory to processor (with operands and results) + +basic operations + +- read — transfers copy of contents of memory location to processor +- write — transfers item of info from processor to a memory location + +## RISC vs CISC instruction sets +(most processors have a compromise) + +RISC (Reduced Instruction Set Computers) + +- simple addressing modes +- each instruction fits in one word +- fewer instructions in set +- arithmetic/logic only on operands in processor registers +- load/store architecture: no direct transfer between memory locations, must be through processor register +- programs tend to be larger in size (more, simpler instructions) + +CISC (Complex Instruction Set Computers) + +- more complex addressing modes, e.g.: + - autoincrement— access operand through effective address in passed register, then increment contents of said register + - autodecrement — contents of passed register are decremented and then used as effective address of operand + - relative — effective address is determined using index mode with PC instead of register +- instructions don’t have to fit into a single word +- more complex instructions +- arithmetic/logic also on both memory locations and registers +- not constrained to load/store architecture + +## Instruction Execution + +the processor has a program counter (PC) register, holds address of next instruction + +processor circuits use info in PC to fetch and execute instructions in order of increasing address (straight-line sequencing) + +executing an instruction + +1. Instruction fetch — instruction fetched from mem location stored in PC and put in instruction register + +2. Instruction execute — instruction is examined and the operation is performed, PC is incremented by 4. + +branch instructions load new address into PC, allow conditional jumping (jump if greater/less than) diff --git a/content/sysarch-notes/Memory types.html b/content/sysarch-notes/Memory types.html @@ -1,3 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="-0.4092537462711334"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-12-17 5:28:58 PM +0000"/><meta name="latitude" content="52.37363590268605"/><meta name="longitude" content="4.836361791607864"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-12-17 6:24:57 PM +0000"/><title>Memory types</title></head><body><div><b>Static memories (SRAM)</b></div><div>circuits that can retain state as long as power is applied</div><div>fast, but cells require several transistors</div><div>one cell has two inverters that are cross-connected — a latch</div><div><img src="Memory%20types.resources/screenshot_2.png" height="411" width="557"/></div><div><br/></div><div>Read operation</div><div><ul><li>word line is activated, closes switches T1 and T2. <br/></li><li>If cell in state 1, signal on b is high and signal on line b’ is low. Vice versa.<br/></li></ul></div><div><br/></div><div>Write operation</div><div><ul><li>sense/write circuit drives bit lines b and b’<br/></li><li>places appropriate value on line b and its complement on b’, activates word line<br/></li><li>forces cell into corresponding state, retains when word line is deactivated<br/></li></ul></div><div><br/></div><div><b>Dynamic memories (DRAM)</b></div><div>do not retain state for a long period unless accessed frequently</div><div>info is stored in form of charge on a capacitor (only for tens of milliseconds)</div><div>contents are periodically refreshed when they are accessed/written to</div><div><br/></div><div>example of single transistor-capacitor DRAM cell:</div><div><img src="Memory%20types.resources/screenshot.png" height="295" width="413"/></div><div><br/></div><div>A full 32M x 8 chip:</div><div><img src="Memory%20types.resources/screenshot_1.png" height="470" width="700"/></div><div>Refresh (and read) operation:</div><div><ul><li>transistor in selected cell is turned on</li><li>sense amplifier on bit line checks if charge in capacitor is above threshold value</li><li>if above, sense amplifier drives bit line to full voltage (1)</li><li>otherwise, pulls bit line to ground level</li></ul><div><br/></div></div><div>Fast page mode:</div><div><ul><li>each sense amplifier is also used as latch</li><li>so when a row address is applied, contents of all cells in the row are loaded into latches</li><li>so all bytes in the row can be transferred sequentially, increasing block transfer speed.<br/></li></ul></div><div><br/></div><div><b>Synchronous DRAMs</b></div><div>operation is synced with a clock signal</div><div>built-in refresh circuitry with a refresh counter to refresh specific rows</div><div><br/></div><div><b>Double-Data-Rate SDRAM</b></div><div>large number of bits are accessed at the same time when a row address is applied</div><div>data are transferred both on rising and falling edges of clock</div><div><br/></div><div><b>Rambus Memory</b></div><div>proprietary</div><div>uses fewer wires with a higher clock speed</div><div>makes use of differential-signaling technique to transfer data</div><div>signals are transmitted using small voltage swings of ±0.1V around reference value</div></body></html>- \ No newline at end of file diff --git a/content/sysarch-notes/Memory types/index.md b/content/sysarch-notes/Memory types/index.md @@ -0,0 +1,69 @@ ++++ +title = 'Memory types' ++++ +# Memory types +## Static memories (SRAM) +circuits that can retain state as long as power is applied + +fast, but cells require several transistors + +one cell has two inverters that are cross-connected — a latch + +![screenshot.png](screenshot-48.png) + +Read operation + +- word line is activated, closes switches T1 and T2. +- If cell in state 1, signal on b is high and signal on line b’ is low. Vice versa. + +Write operation + +- sense/write circuit drives bit lines b and b’ +- places appropriate value on line b and its complement on b’, activates word line +- forces cell into corresponding state, retains when word line is deactivated + +## Dynamic memories (DRAM) +do not retain state for a long period unless accessed frequently + +info is stored in form of charge on a capacitor (only for tens of milliseconds) + +contents are periodically refreshed when they are accessed/written to + +example of single transistor-capacitor DRAM cell: + +![screenshot.png](screenshot-49.png) + +A full 32M x 8 chip: + +![screenshot.png](screenshot-50.png) + +Refresh (and read) operation: +- transistor in selected cell is turned on +- sense amplifier on bit line checks if charge in capacitor is above threshold value +- if above, sense amplifier drives bit line to full voltage (1) +- otherwise, pulls bit line to ground level + +Fast page mode: +- each sense amplifier is also used as latch +- so when a row address is applied, contents of all cells in the row are loaded into latches +- so all bytes in the row can be transferred sequentially, increasing block transfer speed. + +## Synchronous DRAMs +operation is synced with a clock signal + +built-in refresh circuitry with a refresh counter to refresh specific rows + +## Double-Data-Rate SDRAM + +large number of bits are accessed at the same time when a row address is applied + +data are transferred both on rising and falling edges of clock + +## Rambus Memory +proprietary + +uses fewer wires with a higher clock speed + +makes use of differential-signaling technique to transfer data + +signals are transmitted using small voltage swings of ±0.1V around reference value diff --git a/content/sysarch-notes/Memory types.resources/screenshot_2.png b/content/sysarch-notes/Memory types/screenshot-48.png Binary files differ. diff --git a/content/sysarch-notes/Memory types.resources/screenshot.png b/content/sysarch-notes/Memory types/screenshot-49.png Binary files differ. diff --git a/content/sysarch-notes/Memory types.resources/screenshot_1.png b/content/sysarch-notes/Memory types/screenshot-50.png Binary files differ. diff --git a/content/sysarch-notes/Multiplexers.html b/content/sysarch-notes/Multiplexers.html @@ -1,3 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="-0.48866206407547"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-11-09 5:42:46 PM +0000"/><meta name="latitude" content="52.33359935528124"/><meta name="longitude" content="4.867948915268968"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-11-09 5:59:35 PM +0000"/><title>Multiplexers</title></head><body><div>any one of <i>n</i> data inputs can be selected as output. this is done using ‘select’ inputs</div><div>for 2<sup>k </sup>inputs, you need <i>k</i> select inputs</div><div><br/></div><div><img src="Multiplexers.resources/screenshot.png" height="433" width="601"/><img src="Multiplexers.resources/screenshot_1.png" height="113" width="127"/></div><div><br/></div><div><br/></div><div><br/></div></body></html>- \ No newline at end of file diff --git a/content/sysarch-notes/Multiplexers/index.md b/content/sysarch-notes/Multiplexers/index.md @@ -0,0 +1,9 @@ ++++ +title = 'Multiplexers' ++++ +# Multiplexers +any one of *n* data inputs can be selected as output. this is done using ‘select’ inputs + +for 2k inputs, you need *k* select inputs + +![screenshot.png](screenshot-34.png)![screenshot.png](screenshot-35.png) diff --git a/content/sysarch-notes/Multiplexers.resources/screenshot.png b/content/sysarch-notes/Multiplexers/screenshot-34.png Binary files differ. diff --git a/content/sysarch-notes/Multiplexers.resources/screenshot_1.png b/content/sysarch-notes/Multiplexers/screenshot-35.png Binary files differ. diff --git a/content/sysarch-notes/Multiplication of signed integers.html b/content/sysarch-notes/Multiplication of signed integers.html @@ -1,3 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="-0.00303243612870574"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-12-05 5:08:28 PM +0000"/><meta name="latitude" content="52.33420531735815"/><meta name="longitude" content="4.867411570802592"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-12-05 9:49:03 PM +0000"/><title>Multiplication of signed integers</title></head><body><div>Meaning 2’s complement signed ints.</div><div>There’s the shorthand and then there’s the algorithm.</div><div><br/></div><div><span style="font-weight: bold;">Shorthand (same as decimal multiplication)</span></div><div><img src="Multiplication%20of%20signed%20integers.resources/screenshot_2.png" height="230" width="387"/><br/></div><div><br/></div><div><b>Booth’s algorithm:</b></div><div><b><br/></b></div><div>Involves recoding the multiplier (Y in “X times Y”) based on this table, going bitwise left to right.</div><div>If the last bit is a 1, there’s an implied 0 behind it.</div><div><br/></div><div><img src="Multiplication%20of%20signed%20integers.resources/screenshot_3.png" height="206" width="302"/></div><div><br/></div><div>Then you do a table, going bitwise right to left on recoded multiplier. If it’s zero, you shift. If it’s -1, you add -A and shift. If it’s +1, you add A and shift.</div><div><br/></div><div>For example, if given 001111 × 001111:</div><div><br/></div><div>A = 001111</div><div>B = 001111</div><div>-A = 110001</div><div><br/></div><div>Recoded multiplier (B): 0 +1 0 0 0 -1</div><div><table style="border-collapse: collapse; min-width: 100%;"><colgroup><col style="width: 130px;"/><col style="width: 130px;"/><col style="width: 130px;"/></colgroup><tbody><tr><td style="border: 1px solid rgb(219, 219, 219); background-color: rgb(255, 255, 255); width: 130px; padding: 8px;"><div>Product</div></td><td style="border: 1px solid rgb(219, 219, 219); background-color: rgb(255, 255, 255); width: 130px; padding: 8px;"><div>Step description</div></td><td style="border: 1px solid rgb(219, 219, 219); background-color: rgb(255, 255, 255); width: 130px; padding: 8px;"><div>Multiplier bit</div></td></tr><tr><td style="border: 1px solid rgb(219, 219, 219); background-color: rgb(255, 255, 255); width: 130px; padding: 8px;"><div>000000</div></td><td style="border: 1px solid rgb(219, 219, 219); background-color: rgb(255, 255, 255); width: 130px; padding: 8px;"><div>Initialise</div></td><td style="border: 1px solid rgb(219, 219, 219); background-color: rgb(255, 255, 255); width: 130px; padding: 8px;"><div>-</div></td></tr><tr><td style="border: 1px solid rgb(219, 219, 219); background-color: rgb(255, 255, 255); width: 130px; padding: 8px;"><div>110001</div></td><td style="border: 1px solid rgb(219, 219, 219); background-color: rgb(255, 255, 255); width: 130px; padding: 8px;"><div>Add -A</div></td><td style="border: 1px solid rgb(219, 219, 219); background-color: rgb(255, 255, 255); width: 130px; padding: 8px;"><div>-1</div></td></tr><tr><td style="border: 1px solid rgb(219, 219, 219); background-color: rgb(255, 255, 255); width: 130px; padding: 8px;"><div>1110001</div></td><td style="border: 1px solid rgb(219, 219, 219); background-color: rgb(255, 255, 255); width: 130px; padding: 8px;"><div>Shift</div></td><td style="border: 1px solid rgb(219, 219, 219); background-color: rgb(255, 255, 255); width: 130px; padding: 8px;"><div><br/></div></td></tr><tr><td style="border: 1px solid rgb(219, 219, 219); background-color: rgb(255, 255, 255); width: 130px; padding: 8px;"><div>11110001</div></td><td style="border: 1px solid rgb(219, 219, 219); background-color: rgb(255, 255, 255); width: 130px; padding: 8px;"><div>Shift only</div></td><td style="border: 1px solid rgb(219, 219, 219); background-color: rgb(255, 255, 255); width: 130px; padding: 8px;"><div>0</div></td></tr><tr><td style="border: 1px solid rgb(219, 219, 219); background-color: rgb(255, 255, 255); width: 130px; padding: 8px;"><div>111110001</div></td><td style="border: 1px solid rgb(219, 219, 219); background-color: rgb(255, 255, 255); width: 130px; padding: 8px;"><div>Shift only</div></td><td style="border: 1px solid rgb(219, 219, 219); background-color: rgb(255, 255, 255); width: 130px; padding: 8px;"><div>0</div></td></tr><tr><td style="border: 1px solid rgb(219, 219, 219); background-color: rgb(255, 255, 255); width: 130px; padding: 8px;"><div>1111110001</div></td><td style="border: 1px solid rgb(219, 219, 219); background-color: rgb(255, 255, 255); width: 130px; padding: 8px;"><div>Shift only</div></td><td style="border: 1px solid rgb(219, 219, 219); background-color: rgb(255, 255, 255); width: 130px; padding: 8px;"><div>0</div></td></tr><tr><td style="border: 1px solid rgb(219, 219, 219); background-color: rgb(255, 255, 255); width: 130px; padding: 8px;"><div>0011100001</div></td><td style="border: 1px solid rgb(219, 219, 219); background-color: rgb(255, 255, 255); width: 130px; padding: 8px;"><div>Add +A</div></td><td style="border: 1px solid rgb(219, 219, 219); background-color: rgb(255, 255, 255); width: 130px; padding: 8px;"><div>+1</div></td></tr><tr><td style="border: 1px solid rgb(219, 219, 219); background-color: rgb(255, 255, 255); width: 130px; padding: 8px;"><div>00011100001</div></td><td style="border: 1px solid rgb(219, 219, 219); background-color: rgb(255, 255, 255); width: 130px; padding: 8px;"><div>Shift</div></td><td style="border: 1px solid rgb(219, 219, 219); background-color: rgb(255, 255, 255); width: 130px; padding: 8px;"><div><br/></div></td></tr><tr><td style="border: 1px solid rgb(219, 219, 219); background-color: rgb(255, 255, 255); width: 130px; padding: 8px;"><div>000011100001</div></td><td style="border: 1px solid rgb(219, 219, 219); background-color: rgb(255, 255, 255); width: 130px; padding: 8px;"><div>Shift only</div></td><td style="border: 1px solid rgb(219, 219, 219); background-color: rgb(255, 255, 255); width: 130px; padding: 8px;"><div>0</div></td></tr></tbody></table><div>So the final result is 000011100001 (twice as many bits as the terms).</div></div><div><br/></div><div><b>Speeding up the process</b></div><div>Bit-pair recoding of multipliers using Booth recoding:</div><div><img src="Multiplication%20of%20signed%20integers.resources/screenshot.png" height="309" width="521"/></div><div><br/></div><div>For example, for the multiplier 111010:</div><div><br/></div><div><img src="Multiplication%20of%20signed%20integers.resources/screenshot_4.png" height="190" width="464"/></div><div><br/></div><div>To multiply by -1, make 2’s complement. To multiply by -2, add 2’s complement. So now the process is:</div><div><br/></div><div><img src="Multiplication%20of%20signed%20integers.resources/screenshot_1.png" height="400" width="276"/></div><div><br/></div><div>You could also do carry-save addition, which is a crazy-ass circuit where the carries are introduced into the next row at the correct weighted positions.</div><div>Then there’s 3-2 reducer addition: carry-save add summands in groups of 3 to get S and C vectors, group S and C vectors in 3s and carry-save add, etc. until there are only two vectors left. Those are added by carry-save.</div><div><br/></div><div>Also, 4-2 reducer addition:</div><div><ul><li>s, c, and c<sub>out </sub>represent arithmetic sum of five inputs</li><li>output s is the sum variable (XOR of five inputs)</li><li>c<sub>out</sub> is independent of c<sub>in</sub>, only function of four inputs.</li><li>steps:</li><ol><li>c<sub>out</sub> is 1 when two or more inputs  are 1</li><li>other carry (c) is determined to satisfy arithmetic condition</li></ol></ul></div><div><br/></div><div><br/></div></body></html>- \ No newline at end of file diff --git a/content/sysarch-notes/Multiplication of signed integers/index.md b/content/sysarch-notes/Multiplication of signed integers/index.md @@ -0,0 +1,70 @@ ++++ +title = 'Multiplication of signed integers' ++++ +# Multiplication of signed integers +Meaning 2’s complement signed ints. +There’s the shorthand and then there’s the algorithm. + +## Shorthand (same as decimal multiplication) + +![screenshot.png](screenshot-17.png) + +## Booth’s algorithm: +Involves recoding the multiplier (Y in “X times Y”) based on this table, going bitwise left to right. + +If the last bit is a 1, there’s an implied 0 behind it. + +![screenshot.png](screenshot-15.png) + +Then you do a table, going bitwise right to left on recoded multiplier. If it’s zero, you shift. If it’s -1, you add -A and shift. If it’s +1, you add A and shift. + +For example, if given 001111 × 001111: + +``` +A = 001111 +B = 001111 +-A = 110001 +``` + +Recoded multiplier (B): `0 +1 0 0 0 -1` + +| Product | Step description | Multiplier bit | +| --- | --- | --- | +| 000000 | Initialise | - | +| 110001 | Add -A | -1 | +| 1110001 | Shift | | +| 11110001 | Shift only | 0 | +| 111110001 | Shift only | 0 | +| 1111110001 | Shift only | 0 | +| 0011100001 | Add +A | +1 | +| 00011100001 | Shift | | +| 000011100001 | Shift only | 0 | + +So the final result is `000011100001` (twice as many bits as the terms). + +## Speeding up the process +Bit-pair recoding of multipliers using Booth recoding: + +![screenshot.png](screenshot-16.png) + +For example, for the multiplier `111010`: + +![screenshot.png](screenshot-18.png) + +To multiply by -1, make 2’s complement. To multiply by -2, add 2’s complement. So now the process is: + +![screenshot.png](screenshot-14.png) + +You could also do carry-save addition, which is a crazy-ass circuit where the carries are introduced into the next row at the correct weighted positions. + +Then there’s 3-2 reducer addition: carry-save add summands in groups of 3 to get S and C vectors, group S and C vectors in 3s and carry-save add, etc. until there are only two vectors left. Those are added by carry-save. + +Also, 4-2 reducer addition: + +- s, c, and cout represent arithmetic sum of five inputs +- output s is the sum variable (XOR of five inputs) +- cout is independent of cin, only function of four inputs. +- steps: + + 1. cout is 1 when two or more inputs  are 1 + 2. other carry (c) is determined to satisfy arithmetic condition diff --git a/content/sysarch-notes/Multiplication of signed integers.resources/screenshot_1.png b/content/sysarch-notes/Multiplication of signed integers/screenshot-14.png Binary files differ. diff --git a/content/sysarch-notes/Multiplication of signed integers.resources/screenshot_3.png b/content/sysarch-notes/Multiplication of signed integers/screenshot-15.png Binary files differ. diff --git a/content/sysarch-notes/Multiplication of signed integers.resources/screenshot.png b/content/sysarch-notes/Multiplication of signed integers/screenshot-16.png Binary files differ. diff --git a/content/sysarch-notes/Multiplication of signed integers.resources/screenshot_2.png b/content/sysarch-notes/Multiplication of signed integers/screenshot-17.png Binary files differ. diff --git a/content/sysarch-notes/Multiplication of signed integers.resources/screenshot_4.png b/content/sysarch-notes/Multiplication of signed integers/screenshot-18.png Binary files differ. diff --git a/content/sysarch-notes/Multiplying_dividing floats.html b/content/sysarch-notes/Multiplying_dividing floats.html @@ -1,3 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="5.61646738788113e-05"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-12-05 10:08:42 PM +0000"/><meta name="latitude" content="52.37364204200952"/><meta name="longitude" content="4.836135271327998"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-12-05 10:21:41 PM +0000"/><title>Multiplying/dividing floats</title></head><body><div>Multiply:</div><div><ol><li>Add exponents, subtract 127.</li><li>Multiply mantissas and determine sign of the result.</li><li>Normalise resulting value if necessary.</li></ol><div><br/></div></div><div>Divide:</div><div><ol><li>Subtract exponents, add 127.</li><li>Divide mantissas, determine sign of the result.</li><li>Normalise resulting value if necessary.</li></ol><div><br/></div></div><div>Example:</div><div><img src="Multiplying_dividing%20floats.resources/Scannable%20Document%20on%205%20Dec%202017%20at%2023_21_25.png" height="2400" width="1461"/></div><div><br/></div></body></html>- \ No newline at end of file diff --git a/content/sysarch-notes/Multiplying_dividing floats.resources/Scannable Document on 5 Dec 2017 at 23_21_25.png b/content/sysarch-notes/Multiplying_dividing floats/doc.png Binary files differ. diff --git a/content/sysarch-notes/Multiplying_dividing floats/index.md b/content/sysarch-notes/Multiplying_dividing floats/index.md @@ -0,0 +1,17 @@ ++++ +title = 'Multiplying/dividing floats' ++++ +# Multiplying/dividing floats +Multiply: +1. Add exponents, subtract 127. +2. Multiply mantissas and determine sign of the result. +3. Normalise resulting value if necessary. + +Divide: +1. Subtract exponents, add 127. +2. Divide mantissas, determine sign of the result. +3. Normalise resulting value if necessary. + +Example: + +![Scannable Document on 5 Dec 2017 at 23_21_25.png](doc.png) diff --git a/content/sysarch-notes/Multithreading.html b/content/sysarch-notes/Multithreading.html @@ -1,3 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="-0.1619278639554977"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-12-19 6:15:24 PM +0000"/><meta name="latitude" content="52.37356806716691"/><meta name="longitude" content="4.836201981401016"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-12-20 8:08:24 PM +0000"/><title>Multithreading</title></head><body><div>each process in the operating system has a thread</div><div>thread — thread of control whose state consists of contents of program counter and other processor registers (a specific process)</div><div>two or more threads can run on different processors, executing either same part of program on different data, or different parts of a program, or different programs</div><div><br/></div><div>multitasking two or more programs on same processor</div><div>time slicing — OS selects process that’s not blocked and lets it run for a short period of time</div><div>context switching — OS selects a different process at the end of the time slice</div><div>timer interrupt — interrupt-service routine to switch from one process to another</div><div><br/></div><div>hardware multithreading:</div><div><ul><li>processor has several identical sets of registers, each for a different thread</li><li>this includes multiple program counters</li><li>makes context switching simple &amp; fast, just change a hardware pointer to use a different set of registers, in one clock cycle</li></ul><div><br/></div></div><div>coarse-grained multithreading: on a cache miss during Load/Store, switch to a different thread and continue fetching/executing other instructions</div><div>fine-grained/interleaved multithreading: switch threads after every instruction is fetched, increasing processor throughput</div></body></html>- \ No newline at end of file diff --git a/content/sysarch-notes/Multithreading.md b/content/sysarch-notes/Multithreading.md @@ -0,0 +1,27 @@ ++++ +title = 'Multithreading' ++++ +# Multithreading +each process in the operating system has a thread + +thread — thread of control whose state consists of contents of program counter and other processor registers (a specific process) + +two or more threads can run on different processors, executing either same part of program on different data, or different parts of a program, or different programs + +multitasking two or more programs on same processor + +time slicing — OS selects process that’s not blocked and lets it run for a short period of time + +context switching — OS selects a different process at the end of the time slice + +timer interrupt — interrupt-service routine to switch from one process to another + +hardware multithreading: + +- processor has several identical sets of registers, each for a different thread +- this includes multiple program counters +- makes context switching simple & fast, just change a hardware pointer to use a different set of registers, in one clock cycle + +coarse-grained multithreading: on a cache miss during Load/Store, switch to a different thread and continue fetching/executing other instructions + +fine-grained/interleaved multithreading: switch threads after every instruction is fetched, increasing processor throughput diff --git a/content/sysarch-notes/Numeric representations of data types.html b/content/sysarch-notes/Numeric representations of data types.html @@ -1,111 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html> - <head> - <link rel="stylesheet" href="sitewide.css" /> - <meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/> - <meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/> - <meta name="altitude" content="1.558525204658508"/> - <meta name="author" content="Alex Balgavy"/> - <meta name="created" content="2017-11-14 3:02:33 PM +0000"/> - <meta name="latitude" content="52.3330093917089"/> - <meta name="longitude" content="4.865526562425694"/> - <meta name="source" content="desktop.mac"/> - <meta name="updated" content="2017-12-05 10:22:21 PM +0000"/> - <title>Numeric representations of data types</title> - </head> - <body> - <div>Everything’s stored in binary. Obviously. This is computers.</div> - <div><br/></div> - <div><span style="font-weight: bold;">Signed Integers</span></div> - <div>Representing both positive and negative numbers.</div> - <div>Leftmost bit (MSB) tells state of sign flag — 0 for positive and 1 for negative</div> - <div><br/></div> - <div>Systems:</div> - <div> - <ul> - <li>Sign-and-magnitude</li> - <ul> - <li>negative values are represented by changing MSB</li> - <li>two representations for 0 — ±0</li> - </ul> - <li>1’s-complement</li> - <ul> - <li>negative values are bitwise complement of positive</li> - <li>for n-bit, equivalent to subtracting number from 2<span style="vertical-align: super;">n</span>-1</li> - <li>two representations for 0 — ±0</li> - </ul> - <li>2’s-complement</li> - <ul> - <li>1’s-complement; then add 1</li> - <li>in other words: for n-bit, subtract number from 2<span style="font-size: 11.666666030883789px;"><span style="font-size: 11.666666030883789px; vertical-align: super;">n</span></span></li> - <li><span style="font-size: 14px;">one representation for 0</span></li> - <li><span style="font-size: 14px;">can represent -8 in 4 bits</span></li> - </ul> - </ul> - </div> - <div><br/></div> - <div><a href="Addition%20%26%20subtraction%20with%20signed%20integers.html">Arithmetic operations with signed integers.</a></div> - <div><a href="Addition_subtraction%20logic%20unit.html">How to design an actual circuit for this shit.</a></div> - <div><a href="Multiplication%20of%20signed%20integers.html">Multiplication of signed integers</a>.</div> - <div>Division is a pain in the ass, exactly the same as decimal long division. Just with 1s and 0s.</div> - <div><br/></div> - <div><span style="font-weight: bold;">Floats</span></div> - <div>float in binary: sign for number, significant bits, signed scale factor exponent for implied base 2</div> - <div>IEEE standard (32 bit floats) — sign bit, 8-bit signed exponent in excess-127, 23-bit mantissa (fractional)</div> - <div><br/></div> - <div><img src="Numeric%20representations%20of%20data%20types.resources/screenshot.png" height="151" width="494"/><br/></div> - <div><br/></div> - <div>The value stored in exponent is unsigned int E’ = E + 127 (excess-127).</div> - <div>E being unsigned int representation, E’ being excess 127.</div> - <div><br/></div> - <div>Why excess-127? In 32 bits, you have 8 bits for the exponent. With 8 bits, you can represent values 0 to 255. But we want really small numbers, so a negative exponent. So the dudes at IEEE decided to go for -127 to +128. -127 (0) represents 0, 128 (255) represents infinity. So real range is -126 to +127. But the value in the exponent is an unsigned int, from 0 to 255, so the whole thing has to be shifted. Just define 0 to be -127 and you’re done. In other words, if you put a 0 in the exponent, you’re actually representing -127.</div> - <div><br/></div> - <div>Confusing as shit. Basically if you want to write some value, you have to put that value + 127 in the exponent, in binary.</div> - <div><br/></div> - <div>To convert to excess-127:</div> - <div> - <ul> - <li>convert in front of decimal point to binary (divide by 2 until no remainder, bits are in bottom-to-top order)</li> - <li>convert after decimal point to binary (multiply by 2, left of decimal is next fractional 0 or 1, repeat with right of decimal)</li> - <li>normalise it so that it’s of the format “1.<span style="font-style: italic;">M”, </span>note the exponent E</li> - <li>add 127 to E to form E’</li> - <li><span style="font-style: italic;">M</span> is mantissa, E’ is exponent</li> - </ul> - <div><br/></div> - <div>The number is normalised if it’s in the form “1.something × 2<span style="vertical-align: super; font-size: smaller; font-size: smaller;">n</span>”.</div> - </div> - <div><br/></div> - <div>Special values of mantissa:</div> - <div> - <ul> - <li>exponent all 0, mantissa all 0 — 0</li> - <li>exponent all 1, mantissa all 0 — ±Infinity</li> - <li>exponent all 0, mantissa not 0 — denormalised numbers (implied 0 instead of 1)</li> - <li>exponent all 1, mantissa not 0 — Not a Number</li> - </ul> - <div><br/></div> - </div> - <div>All operations use guard bits to keep accuracy. However, to store, you need to remove guard bits (truncate).</div> - <div>Methods:</div> - <div> - <ul> - <li>chopping — literally just slice off any extra bits</li> - <li>von Neumann rounding — if the ones you remove are all 0, you chop them. but if any of them are 1, the LSB of the retained bits is set to 1.</li> - <li>rounding — 1 added to value at LSB of retained if MSB of removed bits is 1. this rounds to an even number.</li> - </ul> - </div> - <div><br/></div> - <div><a href="Adding_subtracting%20floating%20point%20values.html">Adding/subtracting floating point values</a>.</div> - <div><a href="Multiplying_dividing%20floats.html">Multiplying/dividing floating point values.</a></div> - <div><br/></div> - <div><span style="font-weight: bold;">Booleans</span></div> - <div>false — 00000000</div> - <div>true — literally anything else</div> - <div><br/></div> - <div><span style="font-weight: bold;">Characters</span></div> - <div>Common encoding is ASCII. Characters are represented by 7-bit codes. Alphabetic and numeric characters are in increasing sequential order.</div> - <div>Unicode has a large set of international alphabets, with variable width encoding (1-4 bytes, ASCII to Latin/Greek/Cyrillic/Coptic to Chinese/Hindi/tagalog to whatever else)</div> - <div><br/></div> - </body> -</html>- \ No newline at end of file diff --git a/content/sysarch-notes/Numeric representations of data types/index.md b/content/sysarch-notes/Numeric representations of data types/index.md @@ -0,0 +1,87 @@ ++++ +title = 'Numeric representation of data types' ++++ +# Numeric representation of data types +Everything’s stored in binary. Obviously. This is computers. + +## Signed Integers +Representing both positive and negative numbers. + +Leftmost bit (MSB) tells state of sign flag — 0 for positive and 1 for negative + +Systems: + +- Sign-and-magnitude + - negative values are represented by changing MSB + - two representations for 0 — ±0 +- 1’s-complement + - negative values are bitwise complement of positive + - for n-bit, equivalent to subtracting number from 2n-1 + - two representations for 0 — ±0 +- 2’s-complement + - 1’s-complement; then add 1 + - in other words: for n-bit, subtract number from 2n + - one representation for 0 + - can represent -8 in 4 bits + +[Arithmetic operations with signed integers.](../addition-subtraction-with-signed-integers) + +[How to design an actual circuit for this shit.](../addition-subtraction-logic-unit) + +[Multiplication of signed integers](../multiplication-of-signed-integers). + +Division is a pain in the ass, exactly the same as decimal long division. Just with 1s and 0s. + +## Floats + +float in binary: sign for number, significant bits, signed scale factor exponent for implied base 2 + +IEEE standard (32 bit floats) — sign bit, 8-bit signed exponent in excess-127, 23-bit mantissa (fractional) + +![screenshot.png](screenshot-39.png) + +The value stored in exponent is unsigned int E’ = E + 127 (excess-127). +E being unsigned int representation, E’ being excess 127. + +Why excess-127? In 32 bits, you have 8 bits for the exponent. With 8 bits, you can represent values 0 to 255. But we want really small numbers, so a negative exponent. So the dudes at IEEE decided to go for -127 to +128. -127 (0) represents 0, 128 (255) represents infinity. So real range is -126 to +127. But the value in the exponent is an unsigned int, from 0 to 255, so the whole thing has to be shifted. Just define 0 to be -127 and you’re done. In other words, if you put a 0 in the exponent, you’re actually representing -127. + +Confusing as shit. Basically if you want to write some value, you have to put that value + 127 in the exponent, in binary. + +To convert to excess-127: + +- convert in front of decimal point to binary (divide by 2 until no remainder, bits are in bottom-to-top order) +- convert after decimal point to binary (multiply by 2, left of decimal is next fractional 0 or 1, repeat with right of decimal) +- normalise it so that it’s of the format “1.M”, note the exponent E +- add 127 to E to form E’ +- *M* is mantissa, E’ is exponent + +The number is normalised if it’s in the form “1.something × 2ⁿ”. + +Special values of mantissa: + +- exponent all 0, mantissa all 0 — 0 +- exponent all 1, mantissa all 0 — ±Infinity +- exponent all 0, mantissa not 0 — denormalised numbers (implied 0 instead of 1) +- exponent all 1, mantissa not 0 — Not a Number + +All operations use guard bits to keep accuracy. However, to store, you need to remove guard bits (truncate). + +Methods: + +- chopping — literally just slice off any extra bits +- von Neumann rounding — if the ones you remove are all 0, you chop them. but if any of them are 1, the LSB of the retained bits is set to 1. +- rounding — 1 added to value at LSB of retained if MSB of removed bits is 1. this rounds to an even number. + +[Adding/subtracting floating point values](../adding-subtracting-floating-point-values). + +[Multiplying/dividing floating point values.](../multiplying-dividing-floats) + +## Booleans +- false — 00000000 +- true — literally anything else. often, 1 is used. + +## Characters + +Common encoding is ASCII. Characters are represented by 7-bit codes. Alphabetic and numeric characters are in increasing sequential order. + +Unicode has a large set of international alphabets, with variable width encoding (1-4 bytes, ASCII to Latin/Greek/Cyrillic/Coptic to Chinese/Hindi/tagalog to whatever else) diff --git a/content/sysarch-notes/Numeric representations of data types.resources/screenshot.png b/content/sysarch-notes/Numeric representations of data types/screenshot-39.png Binary files differ. diff --git a/content/sysarch-notes/Parallel programming.html b/content/sysarch-notes/Parallel programming.html @@ -1,3 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="0.0130038158968091"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-12-20 9:35:34 PM +0000"/><meta name="latitude" content="52.37351692179788"/><meta name="longitude" content="4.836244283666336"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-12-20 9:42:16 PM +0000"/><title>Parallel programming</title></head><body><div><div><div><b>Thread creation</b><br/></div></div></div>how do we make processors participate in parallel execution?<br/><div><br/></div><div>when a single processor runs a program, there is one active thread of execution control</div><div>for a parallel program, you need independent tasks handled separately by multiple threads of execution control (one for each processor)</div><div>these threads are created explicitly, e.g. using a create_thread routine in a parallel programming library</div><div><br/></div><div><b>Thread synchronisation</b></div><div>how do we ensure that each processor finishes its task before the final result is computed?</div><div><br/></div><div>several methods, usually implemented in library routines</div><div>e.g. barrier — force threads to wait until they all have reached a specific point in the program where there is a call to the barrier routine</div><div><br/></div></body></html>- \ No newline at end of file diff --git a/content/sysarch-notes/Parallel programming.md b/content/sysarch-notes/Parallel programming.md @@ -0,0 +1,20 @@ ++++ +title = 'Parallel programming' ++++ +# Parallel programming +## Thread creation +how do we make processors participate in parallel execution? + +when a single processor runs a program, there is one active thread of execution control + +for a parallel program, you need independent tasks handled separately by multiple threads of execution control (one for each processor) + +these threads are created explicitly, e.g. using a create_thread routine in a parallel programming library + +## Thread synchronisation + +how do we ensure that each processor finishes its task before the final result is computed? + +several methods, usually implemented in library routines + +e.g. barrier — force threads to wait until they all have reached a specific point in the program where there is a call to the barrier routine diff --git a/content/sysarch-notes/Performance considerations.html b/content/sysarch-notes/Performance considerations.html @@ -1,3 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="-0.1842866390943527"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-12-17 8:45:10 PM +0000"/><meta name="latitude" content="52.37353963015489"/><meta name="longitude" content="4.836234900920008"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-12-17 8:50:49 PM +0000"/><title>Performance considerations</title></head><body><div>price/performance ratio — common measure of success</div><div>hit rate — number of hits as a fraction of all attempted accesses</div><div>miss rate — number of misses as fraction of attempted accesses</div><div>miss penalty — total access time seen by processor when miss occurs</div><div><br/></div><div>improvements:</div><div><ul><li>larger cache (increased cost)</li><li>larger block size (only effective up to a certain size, take longer to transfer)</li><li>load-through approach reduces miss penalty</li><li>implement cache on processor chip</li><li>write buffer — temporary storage of write requests, then sent all at once to main memory</li><li>prefetching data into cache</li><li>lockup-free cache — let processor access cache while a miss is being serviced</li></ul></div><div><br/></div></body></html>- \ No newline at end of file diff --git a/content/sysarch-notes/Performance considerations.md b/content/sysarch-notes/Performance considerations.md @@ -0,0 +1,18 @@ ++++ +title = 'Performance considerations' ++++ +# Performance considerations +- price/performance ratio — common measure of success +- hit rate — number of hits as a fraction of all attempted accesses +- miss rate — number of misses as fraction of attempted accesses +- miss penalty — total access time seen by processor when miss occurs + +improvements: + +- larger cache (increased cost) +- larger block size (only effective up to a certain size, take longer to transfer) +- load-through approach reduces miss penalty +- implement cache on processor chip +- write buffer — temporary storage of write requests, then sent all at once to main memory +- prefetching data into cache +- lockup-free cache — let processor access cache while a miss is being serviced diff --git a/content/sysarch-notes/Positional numbering system.html b/content/sysarch-notes/Positional numbering system.html @@ -1,3 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="created" content="2017-11-09 3:09:18 PM +0000"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-11-09 6:26:36 PM +0000"/><title>Positional numbering system</title></head><body><div>Z is a set of {-inf…0…inf} integers<br/></div><div>define an alphabet ∑</div><div>A string X of n elements from ∑: X<span style="vertical-align: sub;">n</span> is in ∑<span style="vertical-align: super;">n</span></div><div>Apply X<span style="vertical-align: sub;">n</span> to a valuation function F</div><div><br/></div><div><br/></div><div>For a base-10 system (radix = 10):</div><div><img src="Positional%20numbering%20system.resources/screenshot_1.png" height="114" width="376"/><br/></div><div><br/></div><div>How do you choose a representation?</div><div><ul><li>representation of special values/cases (e.g. 0)</li><li>range of values that can be represented</li><li>efficiency of implementation (common operations?)</li></ul></div><div><br/></div><div>Unsigned integer representation:</div><div><img src="Positional%20numbering%20system.resources/screenshot.png" height="34" width="409"/><br/></div><div><br/></div><div>Range: 2<span style="vertical-align: super;">n</span> -1 (total 2<span style="vertical-align: super;">n</span>, but one of those is 0)</div><div>Can overflow, so have to detect — carry</div><div><br/></div><div><a href="Positional%20numbering%20system.resources/Page%2028%20-%20Livescribe%203%20Starter%20Notebook.pdf">Page 28 - Livescribe 3 Starter Notebook.pdf</a><a href="Positional%20numbering%20system.resources/Page%2029%20-%20Livescribe%203%20Starter%20Notebook.pdf">Page 29 - Livescribe 3 Starter Notebook.pdf</a></div><div><br/></div></body></html>- \ No newline at end of file diff --git a/content/sysarch-notes/Positional numbering system.resources/Page 28 - Livescribe 3 Starter Notebook.pdf b/content/sysarch-notes/Positional numbering system.resources/Page 28 - Livescribe 3 Starter Notebook.pdf Binary files differ. diff --git a/content/sysarch-notes/Positional numbering system.resources/Page 29 - Livescribe 3 Starter Notebook.pdf b/content/sysarch-notes/Positional numbering system.resources/Page 29 - Livescribe 3 Starter Notebook.pdf Binary files differ. diff --git a/content/sysarch-notes/Positional numbering system.resources/screenshot.png b/content/sysarch-notes/Positional numbering system.resources/screenshot.png Binary files differ. diff --git a/content/sysarch-notes/Positional numbering system.resources/screenshot_1.png b/content/sysarch-notes/Positional numbering system.resources/screenshot_1.png Binary files differ. diff --git a/content/sysarch-notes/Program-controlled I_O.html b/content/sysarch-notes/Program-controlled I_O.html @@ -1,3 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="-0.09754352271556854"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-12-17 1:34:08 PM +0000"/><meta name="latitude" content="52.37355729316155"/><meta name="longitude" content="4.836194589138463"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-12-17 1:34:15 PM +0000"/><title>Program-controlled I/O</title></head><body><div>“a program that performs all functions needed to realise the desired action”</div><div>difference in speed between processor and I/O devices, need to synchronise transfer of data</div><div>solution — signalling protocol (wait for signal from device, a status flag)</div><div>polling — checking the device’s status flag</div><div><br/></div><div><span style="font-weight: bold;">Example: RISC-style I/O</span></div><div>reads from keyboard, echoes back to display. end on newline</div><div><br/></div><ol><li>Point register R2 to address of first location in main memory where read characters will be stored</li><li>Load newline character (terminator) into R3</li><li>Start input loop</li><ol><li>Move keyboard status into R4</li><li>R4 = R4 AND #2</li><ul><li>the KIN status flag is the second byte of the value in R4 — so R4 looks like ...0X or …1X</li><li>#2 is 10 in binary</li><li>ANDing them together gives you the state of the KIN flag (i.e. 0X AND 10 = 0X)</li></ul><li>If [R4] is 0 (KIN is false), jump to step 1 of loop</li></ol><li>Load KBD_DATA byte into R5 (clearing KIN to 0)</li><li>Store R5 into address in R2</li><li>Increment pointer in R2 (to store next character)</li><li>Start output loop</li><ol><li>Load DISP_STATUS byte into R4</li><li>R4 = R4 AND #2</li><ul><li>the DOUT flag is the third byte of the value in R4 — so R4 is either …0XX or …1XX</li><li>#4 is 100 in binary</li><li>ANDing them together gives you the state of the DOUT flag (i.e. 0XX AND 100 = 0XX)</li></ul><li>If [R4] is 0, jump to step 1 of loop</li></ol><li>Store byte in R5 into DISP_DATA</li><li>If the Terminator isn’t in R5 ([R5] ≠ [R3]), jump to step 3 (input loop)</li></ol><div><br/></div><div><br/></div><div><img src="Program-controlled%20I_O.resources/screenshot_1.png" height="256" width="834"/></div><div><br/></div><div><img src="Program-controlled%20I_O.resources/screenshot.png" height="251" width="828"/></div><div><br/></div></body></html>- \ No newline at end of file diff --git a/content/sysarch-notes/Program-controlled I_O/index.md b/content/sysarch-notes/Program-controlled I_O/index.md @@ -0,0 +1,44 @@ ++++ +title = 'Program-controlled I/O' ++++ +# Program-controlled I/O +“a program that performs all functions needed to realise the desired action” + +difference in speed between processor and I/O devices, need to synchronise transfer of data + +solution — signalling protocol (wait for signal from device, a status flag) + +polling — checking the device’s status flag + +## Example: RISC-style I/O +reads from keyboard, echoes back to display. end on newline + +1. Point register R2 to address of first location in main memory where read characters will be stored + +2. Load newline character (terminator) into R3 +3. Start input loop + 1. Move keyboard status into R4 + 2. R4 = R4 AND #2 + - the KIN status flag is the second byte of the value in R4 — so R4 looks like `...0X` or `...1X` + - #2 is 10 in binary + - ANDing them together gives you the state of the KIN flag (i.e. 0X AND 10 = 0X) + + 3. If [R4] is 0 (KIN is false), jump to step 1 of loop +4. Load `KBD_DATA` byte into R5 (clearing KIN to 0) +5. Store R5 into address in R2 +6. Increment pointer in R2 (to store next character) +7. Start output loop + 1. Load `DISP_STATUS` byte into R4 + 2. R4 = R4 AND #2 + + - the DOUT flag is the third byte of the value in R4 — so R4 is either …0XX or …1XX + - #4 is 100 in binary + - ANDing them together gives you the state of the DOUT flag (i.e. 0XX AND 100 = 0XX) + + 3. If [R4] is 0, jump to step 1 of loop +8. Store byte in R5 into `DISP_DATA` +9. If the Terminator isn’t in R5 ([R5] ≠ [R3]), jump to step 3 (input loop) + +![screenshot.png](screenshot-21.png) + +![screenshot.png](screenshot-20.png) diff --git a/content/sysarch-notes/Program-controlled I_O.resources/screenshot.png b/content/sysarch-notes/Program-controlled I_O/screenshot-20.png Binary files differ. diff --git a/content/sysarch-notes/Program-controlled I_O.resources/screenshot_1.png b/content/sysarch-notes/Program-controlled I_O/screenshot-21.png Binary files differ. diff --git a/content/sysarch-notes/Registers and Shift Registers.html b/content/sysarch-notes/Registers and Shift Registers.html @@ -1,3 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="-0.6932544112205505"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-11-09 1:50:55 PM +0000"/><meta name="latitude" content="52.33380577427504"/><meta name="longitude" content="4.868325547039837"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-11-09 2:03:07 PM +0000"/><title>Registers and Shift Registers</title></head><body><div>A flip-flop stores one bit, a register can store many in multiple flip flops.</div><div>A register is just a bunch of flip-flops put together, the operation of which is synced by a common clock.</div><div><br/></div><div><span style="font-weight: bold;">4-bit shift register</span></div><div>Each clock pulse transfers contents (state) of F<span style="vertical-align: sub;">i</span> to F<span style="vertical-align: sub;">i+1 </span>(right shift). </div><div>On each tick, data should only be shifted by one position. This is why gated latches are is not good — value quickly propagates to output, and on to the next gated latch, so no control over number of shifts in one pulse (you’ll end up with all 1s or all 0s).</div><div>Therefore either use master-slave or edge-triggered flip-flops.</div><div><br/></div><div><img src="Registers%20and%20Shift%20Registers.resources/screenshot.png" height="177" width="705"/><br/></div><div><br/></div></body></html>- \ No newline at end of file diff --git a/content/sysarch-notes/Registers and Shift Registers/index.md b/content/sysarch-notes/Registers and Shift Registers/index.md @@ -0,0 +1,16 @@ ++++ +title = 'Registers and Shift Registers' ++++ +# Registers and Shift Registers +A flip-flop stores one bit, a register can store many in multiple flip flops. + +A register is just a bunch of flip-flops put together, the operation of which is synced by a common clock. + +## 4-bit shift register +Each clock pulse transfers contents (state) of Fᵢ to Fᵢ₊₁ (right shift). + +On each tick, data should only be shifted by one position. This is why gated latches are is not good — value quickly propagates to output, and on to the next gated latch, so no control over number of shifts in one pulse (you’ll end up with all 1s or all 0s). + +Therefore either use master-slave or edge-triggered flip-flops. + +![screenshot.png](screenshot-19.png) diff --git a/content/sysarch-notes/Registers and Shift Registers.resources/screenshot.png b/content/sysarch-notes/Registers and Shift Registers/screenshot-19.png Binary files differ. diff --git a/content/sysarch-notes/Representation of data.html b/content/sysarch-notes/Representation of data.html @@ -1,3 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="2.24882698059082"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-11-06 1:44:00 PM +0000"/><meta name="latitude" content="52.33300989593394"/><meta name="longitude" content="4.865525107085234"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-11-06 3:31:32 PM +0000"/><title>Representation of data</title></head><body><div><span style="font-weight: bold;">Representing data</span></div><div>Binary circuits in computers</div><div>Unit of information: bit (binary digit) — 0 or 1 (data values or boolean)</div><div>Bit strings: multiple bits together, which can be given a specific meaning (such as natural numbers)</div><div><br/></div><div><span style="font-weight: bold;">Computing — boolean algebra</span></div><div>we want a computer that can calculate (expression string -&gt; result string(s))</div><div><br/></div><div>operations:</div><div><ul><li>x.y (or x ^ y) — “AND", class of objects with both properties</li><ul><li>x.x— no further information</li><ul><li>x*x = x² = x</li></ul><li>0.x = 0 (annihilator)</li><li>1.x = x (identity)</li></ul><li>x+y (or x v y) — “OR”, merges independent objects</li><li>x+x — no further information</li><ul><li>x+x = x</li><li>0+x = x (identity)</li><li>1+x = 1 (annihilator)</li></ul></ul></div><div><br/></div><div>complements:</div><div><ul><li>if x, then complement is 1-x</li><li>x(1-x) = x-x² = x-x = 0</li><li>1-x = x̄</li></ul><div><br/></div></div><div>therefore, any function ƒ(x) can be written as ƒ(x) = a ⋅ x + b ⋅ (1-x)</div><div>really? let’s try one:</div><blockquote style="margin: 0 0 0 40px; border: none; padding: 0px;"><div>ƒ(x) = a₀ + a₁x</div><div>let b = a₀, a = a₀ + a₁</div><div>∴ ƒ(x) = a ⋅ x + b ⋅ (1-x)</div><div>ƒ(1) = a</div><div>ƒ(0) = b</div><div>ƒ(x) = ƒ(1) ⋅ x + ƒ(0) ⋅ x̄</div><div><br/></div></blockquote><div><b>Truth tables</b><br/></div><div>Binary addition — XOR</div><div>x ⨁ y = x ⋅ ȳ + y ⋅ x̄</div><div><table style="border-collapse: collapse; min-width: 100%;"><colgroup><col style="width: 130px;"/><col style="width: 130px;"/><col style="width: 130px;"/></colgroup><tbody><tr><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>x</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>y</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>⨁</div><div>(carry result)</div></td></tr><tr><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>0</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>0</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>0 0</div></td></tr><tr><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>0</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>1</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>0 1</div></td></tr><tr><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>1</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>0</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>0 1</div></td></tr><tr><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>1</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>1</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>1 0</div></td></tr></tbody></table></div><div>Binary multiplication — AND</div><div>x ⨂ y = x ⋅ y</div><table style="border-collapse: collapse; min-width: 100%;"><colgroup><col style="width: 130px;"/><col style="width: 130px;"/><col style="width: 130px;"/></colgroup><tbody><tr><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>x</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>y</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>⨂</div><div>(carry result)</div></td></tr><tr><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>0</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>0</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>0</div></td></tr><tr><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>0</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>1</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>0 1</div></td></tr><tr><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>1</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>0</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>0 1</div></td></tr><tr><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>1</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>1</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>1 0</div></td></tr></tbody></table><div><br/></div></body></html>- \ No newline at end of file diff --git a/content/sysarch-notes/Representation of data.md b/content/sysarch-notes/Representation of data.md @@ -0,0 +1,68 @@ ++++ +title = 'Representation of data' ++++ +# Representation of data +## Representing data +Binary circuits in computers + +Unit of information: bit (binary digit) — 0 or 1 (data values or boolean) + +Bit strings: multiple bits together, which can be given a specific meaning (such as natural numbers) + +## Computing — boolean algebra +we want a computer that can calculate (expression string → result string(s)) + +operations: + +- x.y (or x ^ y) — “AND", class of objects with both properties + - x.x— no further information + - x*x = x² = x + - 0.x = 0 (annihilator) + - 1.x = x (identity) +- x+y (or x v y) — “OR”, merges independent objects +- x+x — no further information + - x+x = x + - 0+x = x (identity) + - 1+x = 1 (annihilator) + +complements: + +- if x, then complement is 1-x +- x(1-x) = x-x² = x-x = 0 +- 1-x = x̄ + +therefore, any function ƒ(x) can be written as ƒ(x) = a ⋅ x + b ⋅ (1-x) + +can it really? let’s try one: + +``` +ƒ(x) = a₀ + a₁x +let b = a₀, a = a₀ + a₁ +∴ ƒ(x) = a ⋅ x + b ⋅ (1-x) +ƒ(1) = a +ƒ(0) = b +ƒ(x) = ƒ(1) ⋅ x + ƒ(0) ⋅ x̄ +``` + +## Truth tables +Binary addition — XOR + +x ⨁ y = x ⋅ ȳ + y ⋅ x̄ + +| x | y | ⨁<br>(carry result) | +| --- | --- | --- | +| 0 | 0 | 0 0 | +| 0 | 1 | 0 1 | +| 1 | 0 | 0 1 | +| 1 | 1 | 1 0 | + +Binary multiplication — AND + +x ⨂ y = x ⋅ y + +| x | y | ⨂<br>(carry result) | +| --- | --- | --- | +| 0 | 0 | 0 | +| 0 | 1 | 0 1 | +| 1 | 0 | 0 1 | +| 1 | 1 | 1 0 | diff --git a/content/sysarch-notes/Shared-memory multiprocessors.html b/content/sysarch-notes/Shared-memory multiprocessors.html @@ -1,3 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="-0.09378249198198318"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-12-20 8:08:38 PM +0000"/><meta name="latitude" content="52.37354362350699"/><meta name="longitude" content="4.836282974170986"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-12-20 8:52:24 PM +0000"/><title>Shared-memory multiprocessors</title></head><body><div>multiprocessor system has a lot of processors that can do different tasks at the same time</div><div>in a shared-memory multiprocessor, all processors have access to the same memory (probably large)</div><div>memory is distributed across multiple modules, connected by an interconnection network</div><div><br/></div><div>when memory is physically separate processors, all requests go through a network, introducing latency</div><div>if you have the same latency for memory access from all processors, you have a Uniform Memory Access (UMA) multiprocessor (but latency doesn’t magically go away)</div><div><br/></div><div>to improve performance, put a memory module next to each processor</div><div>leads to collection of “nodes”, each with a processor and memory module</div><div>each node is connected to network. no network latency when memory request is local, but if remote, it has to go through the network</div><div>these are Non-Uniform Memory Access (<a href="https://youtu.be/jRx5PrAlUdY?t=1m39s">NUMA</a>) processors</div><div><br/></div><div><img src="Shared-memory%20multiprocessors.resources/screenshot.png" height="676" width="532"/></div><div><br/></div><div><br/></div><div><b>Interconnection networks</b></div><div>suitability is judged in terms of:</div><div><ul><li>bandwidth — capacity of a transmission link to transfer data (bits or bytes per second)</li><li>effective throughput — actual rate of data transfer</li><li>packets — form of data (fixed length and specified format, ideally handled in one clock cycle)</li></ul><div><br/></div></div><div>types commonly used:</div><div><ul><li>buses — set of wires that provide a single shared path for info transfer</li><ul><li>suitable for small number of processors (low contention)</li><li>does not allow new request until the response for the current request is provided</li><li>alternative is split-transaction bus, where request and response can have other events in between them</li></ul><li>ring — point-to-point connections between nodes</li><ul><li>low-latency option 1: bidirectional ring</li><ul><li>halves latency, doubles bandwidth</li><li>increases complexity</li></ul><li>low-latency option 2: hierarchy of rings</li><ul><li>upper-level ring connects lower-level rings</li><li>average latency is reduced</li><li>upper-level ring may become a bottleneck if low-level rings communicate frequently</li></ul></ul><li>crossbar — direct link between any pair of units</li><ul><li>used in UMA multiprocessors to connect processors to memory modules</li><li>enables many simultaneous transfers, if one destination doesn’t get multiple requests</li></ul><li>mesh — like a net over all nodes</li><ul><li>each node connects to its horizontal and vertical neighbours</li><li>wraparound connections can be introduced at edges — “torus”</li></ul><li><br/></li></ul></div><div><br/></div></body></html>- \ No newline at end of file diff --git a/content/sysarch-notes/Shared-memory multiprocessors/index.md b/content/sysarch-notes/Shared-memory multiprocessors/index.md @@ -0,0 +1,50 @@ ++++ +title = 'Shared-memory multiprocessors' ++++ +# Shared-memory multiprocessors +multiprocessor system has a lot of processors that can do different tasks at the same time + +in a shared-memory multiprocessor, all processors have access to the same memory (probably large) + +memory is distributed across multiple modules, connected by an interconnection network + +when memory is physically separate processors, all requests go through a network, introducing latency + +if you have the same latency for memory access from all processors, you have a Uniform Memory Access (UMA) multiprocessor (but latency doesn’t magically go away) + +to improve performance, put a memory module next to each processor +leads to collection of “nodes”, each with a processor and memory module + +each node is connected to network. no network latency when memory request is local, but if remote, it has to go through the network + +these are Non-Uniform Memory Access ([NUMA](https://youtu.be/jRx5PrAlUdY?t=1m39s)) processors + +![screenshot.png](screenshot-25.png) + +## Interconnection networks +suitability is judged in terms of: + +- bandwidth — capacity of a transmission link to transfer data (bits or bytes per second) +- effective throughput — actual rate of data transfer +- packets — form of data (fixed length and specified format, ideally handled in one clock cycle) + +types commonly used: + +- buses — set of wires that provide a single shared path for info transfer + - suitable for small number of processors (low contention) + - does not allow new request until the response for the current request is provided + - alternative is split-transaction bus, where request and response can have other events in between them +- ring — point-to-point connections between nodes + - low-latency option 1: bidirectional ring + - halves latency, doubles bandwidth + - increases complexity + - low-latency option 2: hierarchy of rings + - upper-level ring connects lower-level rings + - average latency is reduced + - upper-level ring may become a bottleneck if low-level rings communicate frequently +- crossbar — direct link between any pair of units + - used in UMA multiprocessors to connect processors to memory modules + - enables many simultaneous transfers, if one destination doesn’t get multiple requests +- mesh — like a net over all nodes + - each node connects to its horizontal and vertical neighbours + - wraparound connections can be introduced at edges — “torus” diff --git a/content/sysarch-notes/Shared-memory multiprocessors.resources/screenshot.png b/content/sysarch-notes/Shared-memory multiprocessors/screenshot-25.png Binary files differ. diff --git a/content/sysarch-notes/Subroutines & the Stack.html b/content/sysarch-notes/Subroutines & the Stack.html @@ -1,3 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="-0.1067453771829605"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-12-11 7:05:54 PM +0000"/><meta name="latitude" content="52.37358216328297"/><meta name="longitude" content="4.836162576452838"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-12-11 10:35:46 PM +0000"/><title>Subroutines &amp; the Stack</title></head><body><div><span style="font-weight: bold;">Subroutines</span></div><div>allow a block of instructions to be called any number of times without having to rewrite it</div><div>calling a subroutine:</div><ol><li>Store contents of PC in link register (contains return address)</li><li>Branch to target address specified by call instruction</li><li>Execute whatever code is there</li><li>When return is called, branch to address in link register</li></ol><div><br style="font-weight: bold;"/></div><div>when nesting, the return address is pushed to the stack by the caller. on return the callee pops the saved return address from the stack into the link register.</div><div><br style="font-weight: bold;"/></div><div>parameters can be passed by:</div><ul><li>registers — convenient &amp; efficient, but may not be enough registers</li><li>processor stack — can pass an arbitrary amount of parameters</li></ul><div><br/></div><div><span style="font-weight: bold;">Stack</span></div><div>a pile of stuff where the stuff can only be added to or taken from the top</div><div>also called LIFO (last-in-first-out)</div><div>push (add elements)</div><div><ol><li>subtract 4 from SP (32-bit)</li><li>move value from register to address stored in SP</li></ol></div><div><br/></div><div>pop (remove elements)</div><div><ol><li>move value from byte at address stored in SP to register</li><li>add 4 to SP (32-bit)</li></ol></div><div><br/></div><div>processor stack is used for storing data, e.g. parameters, registers</div><div>stack pointer register (SP) holds address of top element in stack</div><div>‘grows downwards’ — from high to low addresses, decreasing size</div><div><br/></div><div>stack fame — ‘private workspace’ for a subroutine</div><div><ul><li>allocated at start, deallocated at end of subroutine</li><li>can also be used for local memory variables</li><li>base/frame pointer points to base of current frame, can easily access parameters by using offset(%rbp)</li></ul><div><br/></div></div><div><img src="Subroutines%20&amp;%20the%20Stack.resources/screenshot.png" height="719" width="706"/><br/></div><div><br/></div></body></html>- \ No newline at end of file diff --git a/content/sysarch-notes/Subroutines & the Stack/index.md b/content/sysarch-notes/Subroutines & the Stack/index.md @@ -0,0 +1,47 @@ ++++ +title = 'Subroutines & the stack' ++++ +# Subroutines & the stack +## Subroutines + +allow a block of instructions to be called any number of times without having to rewrite it + +calling a subroutine: +1. Store contents of PC in link register (contains return address) +2. Branch to target address specified by call instruction +3. Execute whatever code is there +4. When return is called, branch to address in link register + +when nesting, the return address is pushed to the stack by the caller. on return the callee pops the saved return address from the stack into the link register. + +parameters can be passed by: + +- registers — convenient & efficient, but may not be enough registers +- processor stack — can pass an arbitrary amount of parameters + +## Stack +a pile of stuff where the stuff can only be added to or taken from the top + +also called LIFO (last-in-first-out) + +push (add elements) +1. subtract 4 from SP (32-bit) +2. move value from register to address stored in SP + +pop (remove elements) +1. move value from byte at address stored in SP to register +2. add 4 to SP (32-bit) + +processor stack is used for storing data, e.g. parameters, registers + +stack pointer register (SP) holds address of top element in stack + +‘grows downwards’ — from high to low addresses, decreasing size + +stack fame — ‘private workspace’ for a subroutine + +- allocated at start, deallocated at end of subroutine +- can also be used for local memory variables +- base/frame pointer points to base of current frame, can easily access parameters by using offset(%rbp) + +![screenshot.png](screenshot-24.png) diff --git a/content/sysarch-notes/Subroutines & the Stack.resources/screenshot.png b/content/sysarch-notes/Subroutines & the Stack/screenshot-24.png Binary files differ. diff --git a/content/sysarch-notes/Superscalar operation.html b/content/sysarch-notes/Superscalar operation.html @@ -1,3 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="-0.16352179646492"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-12-18 1:42:05 PM +0000"/><meta name="latitude" content="52.37361654230003"/><meta name="longitude" content="4.836376305607129"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-12-18 2:05:28 PM +0000"/><title>Superscalar operation</title></head><body><div>for a pipelined processor, the maximum throughput is one instruction per clock cycle</div><div>equip a processor with multiple execution units, each of which is pipelined, and it can handle several instructions in parallel</div><div>the processor is multiple-issue — several instructions execute in same clock cycle but different execution units</div><div>can achieve throughput of more than one instruction per cycle — superscalar processors</div><div><br/></div><div>the fetch unit can get two or more instructions per cycle and put them in an instruction queue</div><div>a dispatch unit takes two or more instructions from front of queue, decodes them, and sends them to execution units</div><div><br/></div><div>superscalar processor with two execution units:</div><div><br/></div><div><img src="Superscalar%20operation.resources/screenshot.png" height="570" width="848"/></div><div><br/></div><div>instruction flow in this processor:</div><div><br/></div><div><img src="Superscalar%20operation.resources/screenshot_1.png" height="366" width="661"/></div><div><br/></div><div>this leads to out-of-order execution, so results have to be saved in temporary registers</div><div>the temporary registers assume the role of the permanent registers and store the result of the instruction</div><div>the commitment unit guarantees in-order commitment using a reorder buffer (queue)</div><div>when an instruction reaches the head of the queue, the data is transferred from a temporary register to a permanent register</div><div><br/></div></body></html>- \ No newline at end of file diff --git a/content/sysarch-notes/Superscalar operation/index.md b/content/sysarch-notes/Superscalar operation/index.md @@ -0,0 +1,31 @@ ++++ +title = 'Superscalar operation' ++++ +# Superscalar operation +for a pipelined processor, the maximum throughput is one instruction per clock cycle + +equip a processor with multiple execution units, each of which is pipelined, and it can handle several instructions in parallel + +the processor is multiple-issue — several instructions execute in same clock cycle but different execution units + +can achieve throughput of more than one instruction per cycle — superscalar processors + +the fetch unit can get two or more instructions per cycle and put them in an instruction queue + +a dispatch unit takes two or more instructions from front of queue, decodes them, and sends them to execution units + +superscalar processor with two execution units: + +![screenshot.png](screenshot-10.png) + +instruction flow in this processor: + +![screenshot.png](screenshot-11.png) + +this leads to out-of-order execution, so results have to be saved in temporary registers + +the temporary registers assume the role of the permanent registers and store the result of the instruction + +the commitment unit guarantees in-order commitment using a reorder buffer (queue) + +when an instruction reaches the head of the queue, the data is transferred from a temporary register to a permanent register diff --git a/content/sysarch-notes/Superscalar operation.resources/screenshot.png b/content/sysarch-notes/Superscalar operation/screenshot-10.png Binary files differ. diff --git a/content/sysarch-notes/Superscalar operation.resources/screenshot_1.png b/content/sysarch-notes/Superscalar operation/screenshot-11.png Binary files differ. diff --git a/content/sysarch-notes/Synthesis of logic functions.html b/content/sysarch-notes/Synthesis of logic functions.html @@ -1,3 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="-0.07592383772134781"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-11-08 1:42:29 PM +0000"/><meta name="latitude" content="52.33351981586082"/><meta name="longitude" content="4.86778768629921"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-11-09 1:00:40 PM +0000"/><title>Synthesis of logic functions</title></head><body><div><span style="font-weight: bold;">Start with a truth table:</span></div><div><div><br/></div><table style="border-collapse: collapse; min-width: 100%;"><colgroup><col style="width: 130px;"/><col style="width: 130px;"/><col style="width: 130px;"/><col style="width: 130px;"/></colgroup><tbody><tr><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div><span style="font-weight: bold;">x₁</span></div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div><span style="font-weight: bold;">x₂</span></div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div><span style="font-weight: bold;">x₃</span></div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div><span style="font-weight: bold;">ƒ₁</span></div></td></tr><tr><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>0</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>0</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div><span style="background-color: rgb(255, 255, 255);">0</span></div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div><span style="background-color: rgb(255, 255, 255);">1</span></div></td></tr><tr><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>0</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>0</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>1</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>1</div></td></tr><tr><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>0</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>1</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>0</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>0</div></td></tr><tr><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>0</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>1</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>1</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>1</div></td></tr><tr><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>1</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>0</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>0</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>0</div></td></tr><tr><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>1</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>0</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>1</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>0</div></td></tr><tr><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>1</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>1</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>0</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>0</div></td></tr><tr><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>1</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>1</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>1</div></td><td style="border: 1px solid rgb(219, 219, 219); width: 130px; padding: 8px;"><div>1</div></td></tr></tbody></table><div><span style="font-weight: bold;">Create a sum-of-products form for each row in which ƒ₁ = 1:</span></div></div><div>(x₁, x₂, x₃) = (0, 0, 0) = 1 —&gt; (x̄₁ x̄₂ x̄₃) = 1</div><div>(x₁, x₂, x₃) = (0, 0, 1) = 1 —&gt; (x̄₁ x̄₂ x₃) = 1</div><div>(x₁, x₂, x₃) = (0, 1, 1) = 1 —&gt; (x̄₁ x₂ x₃) = 1</div><div>(x₁, x₂, x₃) = (1, 1, 1) = 1 —&gt; (x₁ x₂ x₃) = 1</div><div><br/></div><div>All of this combined is therefore:</div><div>∴ƒ₁ = x̄₁ x̄₂ x̄₃ + x̄₁ x̄₂ x₃ + x̄₁ x₂ x₃ + x₁ x₂ x₃</div><div><br/></div><div><span style="font-weight: bold;">Then, minimise the function:</span></div><div>The reason for this is to save components and increase performance.</div><div><br/></div><div>Useful logic rules (can be proved using truth tables):</div><div><br/></div><div><img src="Synthesis%20of%20logic%20functions.resources/screenshot.png" height="254" width="571"/></div><div><br/></div><div><ul/></div><div>Can also use <a href="Karnaugh%20Maps.html">Karnaugh Maps</a></div><div><div><br/></div></div><div>With the function from above:</div><div>ƒ₁ = x̄₁ x̄₂ x̄₃ + x̄₁ x̄₂ x₃ + x̄₁ x₂ x₃ + x₁ x₂ x₃</div><div>= x̄₁ x̄₂ (x̄₃ + x₃) + (x̄₁ + x₁) x₂ x₃</div><div>= x̄₁ x̄₂ (1) + (1) x₂ x₃</div><div>= x̄₁ x̄₂ + x₂ x₃</div><div><br/></div><div><b>Don’t-care conditions</b></div><div>Same values of inputs never occur, so we don’t care about their output. If we use four variables to denote numbers 0..9, six combinations will never be used. Therefore their output is a d.</div><div>We can make the output whatever we want it to be. Make it a 1 whenever it enlarges a group of 1s, as it leads to a minimal logic gate implementation.</div></body></html>- \ No newline at end of file diff --git a/content/sysarch-notes/Synthesis of logic functions/index.md b/content/sysarch-notes/Synthesis of logic functions/index.md @@ -0,0 +1,54 @@ ++++ +title = 'Synthesis of logic functions' ++++ +# Synthesis of logic functions +## Start with a truth table: + +| x₁ | x₂ | x₃ | ƒ₁ | +| --- | --- | --- | --- | +| 0 | 0 | 0 | 1 | +| 0 | 0 | 1 | 1 | +| 0 | 1 | 0 | 0 | +| 0 | 1 | 1 | 1 | +| 1 | 0 | 0 | 0 | +| 1 | 0 | 1 | 0 | +| 1 | 1 | 0 | 0 | +| 1 | 1 | 1 | 1 | + +## Create a sum-of-products form for each row in which ƒ₁ = 1: +``` +(x₁, x₂, x₃) = (0, 0, 0) = 1 —> (x̄₁ x̄₂ x̄₃) = 1 +(x₁, x₂, x₃) = (0, 0, 1) = 1 —> (x̄₁ x̄₂ x₃) = 1 +(x₁, x₂, x₃) = (0, 1, 1) = 1 —> (x̄₁ x₂ x₃) = 1 +(x₁, x₂, x₃) = (1, 1, 1) = 1 —> (x₁ x₂ x₃) = 1 +``` + +All of this combined is therefore: + +``` +∴ƒ₁ = x̄₁ x̄₂ x̄₃ + x̄₁ x̄₂ x₃ + x̄₁ x₂ x₃ + x₁ x₂ x₃ +``` + +## Then, minimise the function: +The reason for this is to save components and increase performance. + +Useful logic rules (can be proved using truth tables): + +![screenshot.png](screenshot-58.png) + +Can also use [Karnaugh Maps](../karnaugh-maps) + +With the function from above: + +``` +ƒ₁ = x̄₁ x̄₂ x̄₃ + x̄₁ x̄₂ x₃ + x̄₁ x₂ x₃ + x₁ x₂ x₃ + = x̄₁ x̄₂ (x̄₃ + x₃) + (x̄₁ + x₁) x₂ x₃ + = x̄₁ x̄₂ (1) + (1) x₂ x₃ + = x̄₁ x̄₂ + x₂ x₃ +``` + +## Don’t-care conditions + +Same values of inputs never occur, so we don’t care about their output. If we use four variables to denote numbers 0..9, six combinations will never be used. Therefore their output is a d. + +We can make the output whatever we want it to be. Make it a 1 whenever it enlarges a group of 1s, as it leads to a minimal logic gate implementation. diff --git a/content/sysarch-notes/Synthesis of logic functions.resources/screenshot.png b/content/sysarch-notes/Synthesis of logic functions/screenshot-58.png Binary files differ. diff --git a/content/sysarch-notes/Take notes on.md b/content/sysarch-notes/Take notes on.md @@ -0,0 +1,11 @@ ++++ +title = 'Take notes on' ++++ +- [X] Chapter 2 (ISAs) +- [X] Appendix E (Assembler, IA64) +- [X] Chapter 5 (Basic Processing Unit) +- [X] Chapter 7.1, 7.2, 7.3 (IO + OS) +- [X] Chapter 3 w/o “all but an example of” (Basic IO) +- [X] Chapter 8.1, 8.2, 8.4-8.7 (Memory & Performance) +- [ ] Chapter 6 except 6.10 (Pipelining & performance) +- [ ] Chapter 12 (Large-scale systems) diff --git a/content/sysarch-notes/The Basic Concept.html b/content/sysarch-notes/The Basic Concept.html @@ -1,3 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="-0.1240958571434021"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-12-18 12:14:11 PM +0000"/><meta name="latitude" content="52.37355272493809"/><meta name="longitude" content="4.836207510443886"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-12-18 12:25:37 PM +0000"/><title>The Basic Concept</title></head><body><div>pipelining — a way of organising concurrent activity in a computer system, where instructions move through the components in an “assembly line” style</div><div>multiple operations happening at the same time</div><div><br/></div><div><img src="The%20Basic%20Concept.resources/screenshot.png" height="364" width="1127"/></div><div><br/></div><div>information (register addresses, immediate data, operations) is held in interstage buffers</div><div>in a five-stage pipeline:</div><div><br/></div><div><img src="The%20Basic%20Concept.resources/screenshot_1.png" height="986" width="686"/></div><div><br/></div><div>but this is an ideal case. if the destination register for instruction I<sub>j</sub> is the source register for instruction I<sub>j+1</sub>, problems happen.</div><div>pipeline has to stall because of the data hazard</div><div><br/></div></body></html>- \ No newline at end of file diff --git a/content/sysarch-notes/The Basic Concept/index.md b/content/sysarch-notes/The Basic Concept/index.md @@ -0,0 +1,19 @@ ++++ +title = 'The basic concept' ++++ +# The basic concept +pipelining — a way of organising concurrent activity in a computer system, where instructions move through the components in an “assembly line” style + +multiple operations happening at the same time + +![screenshot.png](screenshot-22.png) + +information (register addresses, immediate data, operations) is held in interstage buffers + +in a five-stage pipeline: + +![screenshot.png](screenshot-23.png) + +but this is an ideal case. if the destination register for instruction Iᵢ is the source register for instruction Iᵢ₊₁, problems happen. + +pipeline has to stall because of the data hazard diff --git a/content/sysarch-notes/The Basic Concept.resources/screenshot.png b/content/sysarch-notes/The Basic Concept/screenshot-22.png Binary files differ. diff --git a/content/sysarch-notes/The Basic Concept.resources/screenshot_1.png b/content/sysarch-notes/The Basic Concept/screenshot-23.png Binary files differ. diff --git a/content/sysarch-notes/Universal gates.html b/content/sysarch-notes/Universal gates.html @@ -1,3 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="-0.4111878871917725"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-11-09 1:02:32 PM +0000"/><meta name="latitude" content="52.33344889817398"/><meta name="longitude" content="4.868279031033481"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-11-09 1:08:55 PM +0000"/><title>Universal gates</title></head><body><div><span style="font-weight: bold;">NAND (NOT AND)</span></div><div>Acts the same as AND =&gt; NOT</div><div>Any function in sum-of-products (AND-OR) form can be synthesised in NAND-NAND form</div><div><br/></div><div><b><img src="Universal%20gates.resources/screenshot_1.png" height="73" width="170"/><br/></b></div><div><br/></div><div><span style="font-weight: bold;">NOR (NOT OR)</span></div><div>Acts the same as OR =&gt; NOT</div><div>Any function in product-of-sums (OR-AND) form can be synthesised in NOR-NOR form.</div><div><br/></div><div><img src="Universal%20gates.resources/screenshot.png" height="61" width="164"/></div><div><br/></div></body></html>- \ No newline at end of file diff --git a/content/sysarch-notes/Universal gates/index.md b/content/sysarch-notes/Universal gates/index.md @@ -0,0 +1,17 @@ ++++ +title = 'Universal gates' ++++ +# Universal gates +## NAND (NOT AND) +Acts the same as AND => NOT + +Any function in sum-of-products (AND-OR) form can be synthesised in NAND-NAND form + +![screenshot.png](screenshot-57.png) + +## NOR (NOT OR) +Acts the same as OR => NOT + +Any function in product-of-sums (OR-AND) form can be synthesised in NOR-NOR form. + +![screenshot.png](screenshot-56.png) diff --git a/content/sysarch-notes/Universal gates.resources/screenshot.png b/content/sysarch-notes/Universal gates/screenshot-56.png Binary files differ. diff --git a/content/sysarch-notes/Universal gates.resources/screenshot_1.png b/content/sysarch-notes/Universal gates/screenshot-57.png Binary files differ. diff --git a/content/sysarch-notes/Vector (SIMD) processing & GPUs.html b/content/sysarch-notes/Vector (SIMD) processing & GPUs.html @@ -1,3 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="-0.3086079955101013"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-12-19 6:24:57 PM +0000"/><meta name="latitude" content="52.37365102548443"/><meta name="longitude" content="4.836238196735144"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-12-20 8:08:10 PM +0000"/><title>Vector (SIMD) processing &amp; GPUs</title></head><body><div>many programs use loops to operate on vectors of data, so many instructions are executed</div><div>single-instruction multiple-data (SIMD) — use multiple ALUs to operate on multiple data in parallel using a single instruction (as long as operations performed in parallel are independent)</div><div>vector registers hold data for vector instructions — have number of elements L (vector length), determines number of operations that can be done in parallel (multiple ALUs)</div><div><br/></div><div><span style="font-weight: bold;">Vectorisation</span></div><div>in a high-level language, loops working with arrays of numbers are vectorisable if the operations on every pass are independent of all other passes</div><div>a vectorising compiler can recognise those loops and generate vector instructions</div><div>they’re used for stuff like computer graphics and digital signal processing</div><div><br/></div><div><b>GPUs (Graphics Processing Units)</b></div><div>their main purpose in life is to speed up calculations on a large number of floating-points</div><div>a large chip has hundreds of simple cores with floating-point ALUs to do a lot of work in parallel</div><div>a video card has both a GPU and a dedicated memory for it</div><div>they have a special instruction set and hardware architecture</div><div><br/></div></body></html>- \ No newline at end of file diff --git a/content/sysarch-notes/Vector (SIMD) processing & GPUs.md b/content/sysarch-notes/Vector (SIMD) processing & GPUs.md @@ -0,0 +1,26 @@ ++++ +title = 'Vector (SIMD) processing & GPUs' ++++ +# Vector (SIMD) processing & GPUs +many programs use loops to operate on vectors of data, so many instructions are executed + +single-instruction multiple-data (SIMD) — use multiple ALUs to operate on multiple data in parallel using a single instruction (as long as operations performed in parallel are independent) + +vector registers hold data for vector instructions — have number of elements L (vector length), determines number of operations that can be done in parallel (multiple ALUs) + +## Vectorisation + +in a high-level language, loops working with arrays of numbers are vectorisable if the operations on every pass are independent of all other passes + +a vectorising compiler can recognise those loops and generate vector instructions + +they’re used for stuff like computer graphics and digital signal processing + +## GPUs (Graphics Processing Units) + +their main purpose in life is to speed up calculations on a large number of floating-points + +a large chip has hundreds of simple cores with floating-point ALUs to do a lot of work in parallel + +a video card has both a GPU and a dedicated memory for it +they have a special instruction set and hardware architecture diff --git a/content/sysarch-notes/_index.md b/content/sysarch-notes/_index.md @@ -0,0 +1,115 @@ ++++ +title = 'Systems Architecture' ++++ + +# Systems Architecture + +1. [Intro: Laws of Computing](empirical-laws-of-computing) + +2. Digital Logic + + - Boolean Algebra + - [Representation of data (algebra, truth tables)](representation-of-data) + - [Logic function synthesis](synthesis-of-logic-functions) + - [Minimisation using Karnaugh maps](karnaugh-maps) + - Logic gates + - [Basic (AND, OR, NOT, XOR)](basic-logic-gates) + - [Universal (NAND, NOR)](universal-gates) + - Combinatorial circuits (output depends only on current input) + - [Decoders](decoders) + - [Multiplexers](multiplexers) + - Sequential circuits (output also depends on previous inputs - system state) + - [Flip-flops](flip-flops) + - SR Latch + - Gated SR Latch + - Gated D latch + - T flip-flop + - Master-slave flip-flop + - [Registers, shift registers](registers-and-shift-registers) + - [Counters](counters) + +3. Digital Data + + - [Positional numbering system](positional-numbering-system) + - [Conversion between bases](conversion-between-bases) + - [Numeric representations of data types](numeric-representations-of-data-types) + - Integers arithmetic + - [Addition & subtraction with signed integers](addition-subtraction-with-signed-integers) + - [Addition/subtraction logic unit](addition-subtraction-logic-unit) + - [Multiplication of signed integers](multiplication-of-signed-integers) + - Floating point arithmetic + - [Adding/subtracting floating point values](adding-subtracting-floating-point-values). + - [Multiplying/dividing floating point values.](multiplying-dividing-floats) + +4. ISAs + + 1. [Memory locations & addresses](memory-locations-addresses) + + 2. [Memory operations & instructions](memory-operations-instructions) + + 3. [Addressing modes](addressing-modes) + + 4. [Subroutines & the Stack](subroutines-the-stack) + +5. Basic processing unit + + 1. [Instruction execution](instruction-execution) + + 2. [Hardware components](hardware-components) + + 3. [Data path & instructions](data-path-instructions) + +6. Pipelining + + 1. [The Basic Concept](the-basic-concept) + + 2. Hazards + + 1. [Data dependencies](data-dependencies) + + 2. [Memory delays](memory-delays) + + 3. [Branch delays](branch-delays) + + 3. [Superscalar operation](superscalar-operation) + +7. IO + + 1. [Buses](buses) + + 2. [Accessing I/O devices](accessing-i-o-devices) + + 3. Basic approaches: + + - [Program-controlled](program-controlled-i-o) + - [Interrupts](interrupts) + +8. Memory + + 1. [Basic concepts](basic-concepts) + + 2. [Internal organisation of memory chips](internal-organisation-of-memory-chips) + + 3. [Memory types](memory-types) + + 4. [Direct Memory Access (DMA)](direct-memory-access-dma) + + 5. [Memory Hierarchy](memory-hierarchy) + + 6. [Cache memory](cache-memory) + + 7. [Mapping functions](mapping-functions) + + 8. [Performance considerations](performance-considerations) + +9. Large-scale systems (parallel processing & performance) + + 1. [Multithreading](multithreading) + + 2. [Vector (SIMD) processing & GPUs](vector-simd-processing-gpus) + + 3. [Shared-memory multiprocessors](shared-memory-multiprocessors) + + 4. [Cache coherence](cache-coherence) + + 5. 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at end of file diff --git a/content/sysarch-notes/font/fontawesome-webfont.ttf b/content/sysarch-notes/font/fontawesome-webfont.ttf Binary files differ. diff --git a/content/sysarch-notes/font/fontawesome-webfont.woff b/content/sysarch-notes/font/fontawesome-webfont.woff Binary files differ. diff --git a/content/sysarch-notes/index.html b/content/sysarch-notes/index.html @@ -1,139 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> -<html> -<head> - <link rel="stylesheet" href="sitewide.css" /> - <meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/> - <meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/> - <meta name="altitude" content="-0.3392036855220795"/> - <meta name="author" content="Alex Balgavy"/> - <meta name="created" content="2017-11-09 6:01:39 PM +0000"/> - <meta name="latitude" content="52.33345929759531"/> - <meta name="longitude" content="4.868072715799867"/> - <meta name="source" content="desktop.mac"/> - <meta name="updated" content="2017-12-20 9:45:29 PM +0000"/> - <title>TOC: Systems Architecture</title> -</head> -<body> - <nav> -<a href="http://thezeroalpha.github.io">Homepage</a> -</nav> - - <h1>Systems Architecture Notes</h1> - <h3>Alex Balgavy</h3> - <div> - <ol> - <li><a href="Empirical%20Laws%20of%20Computing.html">Intro: Laws of Computing</a></li> - <li>Digital Logic</li> - <ul> - <li>Boolean Algebra</li> - </ul> - <ol> - <ul> - <li><a href="Representation%20of%20data.html">Representation of data (algebra, truth tables)</a></li> - <li><a href="Synthesis%20of%20logic%20functions.html">Logic function synthesis</a></li> - <li><a href="Karnaugh%20Maps.html">Minimisation using Karnaugh maps</a></li> - </ul> - </ol> - <ul> - <li>Logic gates</li> - <ul> - <li><a href="Basic%20logic%20gates.html">Basic (AND, OR, NOT, XOR)</a></li> - <li><a href="Universal%20gates.html">Universal (NAND, NOR)</a></li> - </ul> - <li>Combinatorial circuits (output depends only on current input)</li> - <ul> - <li><a href="Decoders.html">Decoders</a></li> - <li><a href="Multiplexers.html">Multiplexers</a></li> - </ul> - <li>Sequential circuits (output also depends on previous inputs - system state)</li> - <ul> - <li><a href="Flip-Flops.html">Flip-flops</a></li> - <ul> - <li>SR Latch</li> - <li>Gated SR Latch</li> - <li>Gated D latch</li> - <li>T flip-flop</li> - <li>Master-slave flip-flop</li> - </ul> - <li><a href="Registers%20and%20Shift%20Registers.html">Registers, shift registers</a></li> - <li><a href="Counters.html">Counters</a></li> - </ul> - </ul> - <li>Digital Data</li> - <ul> - <li><a href="Positional%20numbering%20system.html">Positional numbering system</a></li> - <li><a href="Conversion%20between%20bases.html">Conversion between bases</a></li> - <li><a href="Numeric%20representations%20of%20data%20types.html">Numeric representations of data types</a></li> - <ul> - <li>Integers arithmetic</li> - <ul> - <li><a href="Addition%20%26%20subtraction%20with%20signed%20integers.html">Addition &amp; subtraction with signed integers</a></li> - <li><a href="Addition_subtraction%20logic%20unit.html">Addition/subtraction logic unit</a></li> - <li><a href="Multiplication%20of%20signed%20integers.html">Multiplication of signed integers</a></li> - </ul> - <li>Floating point arithmetic</li> - <ul> - <li><a href="Adding_subtracting%20floating%20point%20values.html">Adding/subtracting floating point values</a>.</li> - <li><a href="Multiplying_dividing%20floats.html">Multiplying/dividing floating point values.</a></li> - </ul> - </ul> - </ul> - <li>ISAs</li> - <ol> - <li><a href="Memory%20locations%20%26%20addresses.html">Memory locations &amp; addresses</a></li> - <li><a href="Memory%20operations%20%26%20instructions.html">Memory operations &amp; instructions</a></li> - <li><a href="Addressing%20modes.html">Addressing modes</a></li> - <li><a href="Subroutines%20%26%20the%20Stack.html">Subroutines &amp; the Stack</a></li> - </ol> - <li>Basic processing unit</li> - <ol> - <li><a href="Instruction%20execution.html">Instruction execution</a></li> - <li><a href="Hardware%20components.html">Hardware components</a></li> - <li><a href="Data%20path%20%26%20instructions.html">Data path &amp; instructions</a></li> - </ol> - <li>Pipelining</li> - <ol> - <li><a href="The%20Basic%20Concept.html">The Basic Concept</a></li> - <li>Hazards</li> - <ol> - <li><a href="Data%20dependencies.html">Data dependencies</a></li> - <li><a href="Memory%20delays.html">Memory delays</a></li> - <li><a href="Branch%20delays.html">Branch delays</a></li> - </ol> - <li><a href="Superscalar%20operation.html">Superscalar operation</a></li> - </ol> - <li>IO</li> - <ol> - <li><a href="Buses.html">Buses</a></li> - <li><a href="Accessing%20I_O%20devices.html">Accessing I/O devices</a></li> - <li>Basic approaches:</li> - <ul> - <li><a href="Program-controlled%20I_O.html">Program-controlled</a></li> - <li><a href="Interrupts.html">Interrupts</a></li> - </ul> - </ol> - <li>Memory</li> - <ol> - <li><a href="Basic%20concepts.html">Basic concepts</a></li> - <li><a href="Internal%20organisation%20of%20memory%20chips.html">Internal organisation of memory chips</a></li> - <li><a href="Memory%20types.html">Memory types</a></li> - <li><a href="Direct%20Memory%20Access%20%28DMA%29.html">Direct Memory Access (DMA)</a></li> - <li><a href="Memory%20Hierarchy.html">Memory Hierarchy</a></li> - <li><a href="Cache%20memory.html">Cache memory</a></li> - <li><a href="Mapping%20functions.html">Mapping functions</a></li> - <li><a href="Performance%20considerations.html">Performance considerations</a></li> - </ol> - <li>Large-scale systems (parallel processing &amp; performance)</li> - <ol> - <li><a href="Multithreading.html">Multithreading</a></li> - <li><a href="Vector%20%28SIMD%29%20processing%20%26%20GPUs.html">Vector (SIMD) processing &amp; GPUs</a></li> - <li><a href="Shared-memory%20multiprocessors.html">Shared-memory multiprocessors</a></li> - <li><a href="Cache%20coherence.html">Cache coherence</a></li> - <li><a href="Parallel%20programming.html">Parallel programming</a></li> - </ol> - </ol> - </div> - <div><br/></div> -</body> -</html> diff --git a/content/sysarch-notes/positional-numbering-system.md b/content/sysarch-notes/positional-numbering-system.md @@ -0,0 +1,36 @@ ++++ +title = 'Positional numbering system' +template = 'page-math.html' ++++ +# Positional numbering system +Z is a set of {-inf…0…inf} integers + +define an alphabet ∑ + +A string X of n elements from ∑: Xn is in ∑n + +Apply Xn to a valuation function F + +For a base-10 system (radix = 10): + +$ +\begin{aligned} +277_{10} &= \begin{array}{c|c|c} 10^{2} & 10^{1} & 10^{0} \\\\ \\hline 2 & 7 & 7 \end{array} \\\\ +&= 2(10^{2}) + 7(10) + 7(1) +\end{aligned} +$ + +How do you choose a representation? +- representation of special values/cases (e.g. 0) +- range of values that can be represented +- efficiency of implementation (common operations?) + +Unsigned integer representation: + +$ +F : x_{n-1} \cdot 2^{n-1} + x_{n-2} \cdot 2^{n-2} + \dots + x_{0} \cdot 2^{0} +$ + +Range: 2ⁿ-1 (total 2ⁿ, but one of those is 0) + +Can overflow, so have to detect — carry diff --git a/content/sysarch-notes/sitewide.css b/content/sysarch-notes/sitewide.css @@ -1,30 +0,0 @@ -@charset 'UTF-8'; -@font-face{font-family:'FontAwesome';src:url('font/fontawesome-webfont.eot?v=4.0.1');src:url('font/fontawesome-webfont.eot?#iefix&v=4.0.1') format('embedded-opentype'),url('font/fontawesome-webfont.woff?v=4.0.1') format('woff'),url('font/fontawesome-webfont.ttf?v=4.0.1') format('truetype'),url('font/fontawesome-webfont.svg?v=4.0.1#fontawesomeregular') format('svg');font-weight:normal;font-style:normal} - -body { - margin: 0px; - padding: 1em; - background: #f3f2ed; - font-family: 'Lato', sans-serif; - font-size: 12pt; - font-weight: 300; - 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