index.md (1514B)
1 +++ 2 title = 'Buses' 3 +++ 4 # Buses 5 ## Bus Structure 6 7 bus — commonly used interconnection network between processor, memory, and I/O devices 8 9 three sets of lines (wires) to carry address, data, and control signals 10 11 - address lines — processor places address on it, decoders of all devices on the bus analyse it, the one that recognises the address responds to commands on control line 12 - control lines — used by processor to request read/write 13 - data lines — used for transferring requested data 14 15 when processor places address on address line, decoders of all devices on the bus analyse it 16 17 the device that recognises the address responds to the commands on the control lines 18 19 ## Bus operation 20 bus protocol — set of rules governing how it’s used by various devices 21 22 rules are implemented by control signals 23 24 e.g. a R/W̄ control line — read when 1, write when 0 25 26 if multiple devices request to access the bus, the decision is made by an arbiter circuit 27 28 Synchronous bus: all devices get timing info from bus clock control line 29 30 - simple, but it’s got problems 31 - transfer has to be done in one clock cycle, so clock period has to accommodate slowest component 32 - processor can’t determine whether device actually responded 33 - so many designs include control signals representing a response from a device 34 35  36 37 Asynchronous bus: based on use of a handshake protocol between master and slave (exchange of command and response signals) 38 39 