Buses.html (2735B)
1 <?xml version="1.0" encoding="UTF-8"?> 2 <!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> 3 <html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="0.2139492332935333"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-12-16 11:12:21 PM +0000"/><meta name="latitude" content="52.37346668956735"/><meta name="longitude" content="4.836244824703589"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-12-16 11:42:23 PM +0000"/><title>Buses</title></head><body><div><span style="font-weight: bold;">Bus Structure</span></div><div>bus — commonly used interconnection network between processor, memory, and I/O devices</div><div>three sets of lines (wires) to carry address, data, and control signals</div><div><ul><li>address lines — processor places address on it, decoders of all devices on the bus analyse it, the one that recognises the address responds to commands on control line</li><li>control lines — used by processor to request read/write</li><li>data lines — used for transferring requested data</li></ul></div><div><br/></div><div>when processor places address on address line, decoders of all devices on the bus analyse it</div><div>the device that recognises the address responds to the commands on the control lines</div><div><br/></div><div><span style="font-weight: bold;">Bus operation</span></div><div>bus protocol — set of rules governing how it’s used by various devices</div><div>rules are implemented by control signals</div><div>e.g. a R/W̄ control line — read when 1, write when 0</div><div><br/></div><div>if multiple devices request to access the bus, the decision is made by an arbiter circuit</div><div><br/></div><div>Synchronous bus: all devices get timing info from bus clock control line</div><div><ul><li>simple, but it’s got problems</li><li>transfer has to be done in one clock cycle, so clock period has to accommodate slowest component</li><li>processor can’t determine whether device actually responded</li><li>so many designs include control signals representing a response from a device</li></ul><div><img src="Buses.resources/screenshot.png" height="432" width="589"/><br/></div></div><div><br/></div><div>Asynchronous bus: based on use of a handshake protocol between master and slave (exchange of command and response signals)</div><div><br/></div><div><img src="Buses.resources/screenshot_1.png" height="456" width="647"/><br/></div><div><br/></div><div><br/></div></body></html>