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1 <?xml version="1.0" encoding="UTF-8"?> 2 <!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> 3 <html> 4 <head> 5 <link rel="stylesheet" href="sitewide.css" /> 6 <meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/> 7 <meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/> 8 <meta name="altitude" content="-0.3392036855220795"/> 9 <meta name="author" content="Alex Balgavy"/> 10 <meta name="created" content="2017-11-09 6:01:39 PM +0000"/> 11 <meta name="latitude" content="52.33345929759531"/> 12 <meta name="longitude" content="4.868072715799867"/> 13 <meta name="source" content="desktop.mac"/> 14 <meta name="updated" content="2017-12-20 9:45:29 PM +0000"/> 15 <title>TOC: Systems Architecture</title> 16 </head> 17 <body> 18 <nav> 19 <a href="http://thezeroalpha.github.io">Homepage</a> 20 </nav> 21 22 <h1>Systems Architecture Notes</h1> 23 <h3>Alex Balgavy</h3> 24 <div> 25 <ol> 26 <li><a href="Empirical%20Laws%20of%20Computing.html">Intro: Laws of Computing</a></li> 27 <li>Digital Logic</li> 28 <ul> 29 <li>Boolean Algebra</li> 30 </ul> 31 <ol> 32 <ul> 33 <li><a href="Representation%20of%20data.html">Representation of data (algebra, truth tables)</a></li> 34 <li><a href="Synthesis%20of%20logic%20functions.html">Logic function synthesis</a></li> 35 <li><a href="Karnaugh%20Maps.html">Minimisation using Karnaugh maps</a></li> 36 </ul> 37 </ol> 38 <ul> 39 <li>Logic gates</li> 40 <ul> 41 <li><a href="Basic%20logic%20gates.html">Basic (AND, OR, NOT, XOR)</a></li> 42 <li><a href="Universal%20gates.html">Universal (NAND, NOR)</a></li> 43 </ul> 44 <li>Combinatorial circuits (output depends only on current input)</li> 45 <ul> 46 <li><a href="Decoders.html">Decoders</a></li> 47 <li><a href="Multiplexers.html">Multiplexers</a></li> 48 </ul> 49 <li>Sequential circuits (output also depends on previous inputs - system state)</li> 50 <ul> 51 <li><a href="Flip-Flops.html">Flip-flops</a></li> 52 <ul> 53 <li>SR Latch</li> 54 <li>Gated SR Latch</li> 55 <li>Gated D latch</li> 56 <li>T flip-flop</li> 57 <li>Master-slave flip-flop</li> 58 </ul> 59 <li><a href="Registers%20and%20Shift%20Registers.html">Registers, shift registers</a></li> 60 <li><a href="Counters.html">Counters</a></li> 61 </ul> 62 </ul> 63 <li>Digital Data</li> 64 <ul> 65 <li><a href="Positional%20numbering%20system.html">Positional numbering system</a></li> 66 <li><a href="Conversion%20between%20bases.html">Conversion between bases</a></li> 67 <li><a href="Numeric%20representations%20of%20data%20types.html">Numeric representations of data types</a></li> 68 <ul> 69 <li>Integers arithmetic</li> 70 <ul> 71 <li><a href="Addition%20%26%20subtraction%20with%20signed%20integers.html">Addition & subtraction with signed integers</a></li> 72 <li><a href="Addition_subtraction%20logic%20unit.html">Addition/subtraction logic unit</a></li> 73 <li><a href="Multiplication%20of%20signed%20integers.html">Multiplication of signed integers</a></li> 74 </ul> 75 <li>Floating point arithmetic</li> 76 <ul> 77 <li><a href="Adding_subtracting%20floating%20point%20values.html">Adding/subtracting floating point values</a>.</li> 78 <li><a href="Multiplying_dividing%20floats.html">Multiplying/dividing floating point values.</a></li> 79 </ul> 80 </ul> 81 </ul> 82 <li>ISAs</li> 83 <ol> 84 <li><a href="Memory%20locations%20%26%20addresses.html">Memory locations & addresses</a></li> 85 <li><a href="Memory%20operations%20%26%20instructions.html">Memory operations & instructions</a></li> 86 <li><a href="Addressing%20modes.html">Addressing modes</a></li> 87 <li><a href="Subroutines%20%26%20the%20Stack.html">Subroutines & the Stack</a></li> 88 </ol> 89 <li>Basic processing unit</li> 90 <ol> 91 <li><a href="Instruction%20execution.html">Instruction execution</a></li> 92 <li><a href="Hardware%20components.html">Hardware components</a></li> 93 <li><a href="Data%20path%20%26%20instructions.html">Data path & instructions</a></li> 94 </ol> 95 <li>Pipelining</li> 96 <ol> 97 <li><a href="The%20Basic%20Concept.html">The Basic Concept</a></li> 98 <li>Hazards</li> 99 <ol> 100 <li><a href="Data%20dependencies.html">Data dependencies</a></li> 101 <li><a href="Memory%20delays.html">Memory delays</a></li> 102 <li><a href="Branch%20delays.html">Branch delays</a></li> 103 </ol> 104 <li><a href="Superscalar%20operation.html">Superscalar operation</a></li> 105 </ol> 106 <li>IO</li> 107 <ol> 108 <li><a href="Buses.html">Buses</a></li> 109 <li><a href="Accessing%20I_O%20devices.html">Accessing I/O devices</a></li> 110 <li>Basic approaches:</li> 111 <ul> 112 <li><a href="Program-controlled%20I_O.html">Program-controlled</a></li> 113 <li><a href="Interrupts.html">Interrupts</a></li> 114 </ul> 115 </ol> 116 <li>Memory</li> 117 <ol> 118 <li><a href="Basic%20concepts.html">Basic concepts</a></li> 119 <li><a href="Internal%20organisation%20of%20memory%20chips.html">Internal organisation of memory chips</a></li> 120 <li><a href="Memory%20types.html">Memory types</a></li> 121 <li><a href="Direct%20Memory%20Access%20%28DMA%29.html">Direct Memory Access (DMA)</a></li> 122 <li><a href="Memory%20Hierarchy.html">Memory Hierarchy</a></li> 123 <li><a href="Cache%20memory.html">Cache memory</a></li> 124 <li><a href="Mapping%20functions.html">Mapping functions</a></li> 125 <li><a href="Performance%20considerations.html">Performance considerations</a></li> 126 </ol> 127 <li>Large-scale systems (parallel processing & performance)</li> 128 <ol> 129 <li><a href="Multithreading.html">Multithreading</a></li> 130 <li><a href="Vector%20%28SIMD%29%20processing%20%26%20GPUs.html">Vector (SIMD) processing & GPUs</a></li> 131 <li><a href="Shared-memory%20multiprocessors.html">Shared-memory multiprocessors</a></li> 132 <li><a href="Cache%20coherence.html">Cache coherence</a></li> 133 <li><a href="Parallel%20programming.html">Parallel programming</a></li> 134 </ol> 135 </ol> 136 </div> 137 <div><br/></div> 138 </body> 139 </html>