commit 5a6b02eefb94e16c8d7a7f6e901efe35e4b27075
parent 9473b0c84bebf64c38967268d10157477a7362b4
Author: Alex Balgavy <alex@balgavy.eu>
Date: Mon, 1 Nov 2021 17:47:56 +0100
Finalize AOS notes
Diffstat:
2 files changed, 42 insertions(+), 0 deletions(-)
diff --git a/content/aos-notes/_index.md b/content/aos-notes/_index.md
@@ -10,3 +10,4 @@ title = 'Advanced OS'
- [User mode](user-mode)
- [Paging](paging)
- [Multiprocessing](multiprocessing)
+- [Multicore](multicore)
diff --git a/content/aos-notes/multicore.md b/content/aos-notes/multicore.md
@@ -0,0 +1,41 @@
++++
+title = 'Multicore'
++++
+# Multicore
+Multicores:
+- explicit parallel execution in processor chip
+- share some resources (cache, mem, IO, ...)
+- kernel needs to:
+ - start/stop cores when needed
+ deal with consistency/scalability
+ - schedule work on cores
+
+## Turning on x86 cores:
+BIOS starts one core (the bootstrapping processor, "BSP")
+
+BSP starts other cores via special interrupt.
+
+PIC: programmable interrupt controller, raises interrupt on CPU
+
+APIC: interrupt reporting, thermal management, performance monitoring, inter-processor interrupts
+
+Starting other processors:
+- go to ACPI (set up in predefined memory region by BIOS)
+- ACPI contains info also about APIC
+- root system descriptor table (RSD) contains pointer to MADT (multiple APIC descriptor table)
+- RSDP → RSDT → MADT → LAPIC
+
+Enabling APIC:
+- find where memory mapped: stored in MADT, same between cores
+- set up spurious interrupt vector
+- disable master & slave 8259 PIC: mask all interrupts, remap IRQs to above vector 32
+
+Sending IPIs:
+- need to know destination core APIC ID (list of IDs is in MADT)
+- write to LAPIC interrupt command register
+
+Starting APs (application processors)
+- send INIT IPI
+- send start-up IPI, starts at given entry point
+- think about what this means for the kernel (e.g. stack)
+
