Superscalar operation.html (2323B)
1 <?xml version="1.0" encoding="UTF-8"?> 2 <!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> 3 <html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="-0.16352179646492"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-12-18 1:42:05 PM +0000"/><meta name="latitude" content="52.37361654230003"/><meta name="longitude" content="4.836376305607129"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-12-18 2:05:28 PM +0000"/><title>Superscalar operation</title></head><body><div>for a pipelined processor, the maximum throughput is one instruction per clock cycle</div><div>equip a processor with multiple execution units, each of which is pipelined, and it can handle several instructions in parallel</div><div>the processor is multiple-issue — several instructions execute in same clock cycle but different execution units</div><div>can achieve throughput of more than one instruction per cycle — superscalar processors</div><div><br/></div><div>the fetch unit can get two or more instructions per cycle and put them in an instruction queue</div><div>a dispatch unit takes two or more instructions from front of queue, decodes them, and sends them to execution units</div><div><br/></div><div>superscalar processor with two execution units:</div><div><br/></div><div><img src="Superscalar%20operation.resources/screenshot.png" height="570" width="848"/></div><div><br/></div><div>instruction flow in this processor:</div><div><br/></div><div><img src="Superscalar%20operation.resources/screenshot_1.png" height="366" width="661"/></div><div><br/></div><div>this leads to out-of-order execution, so results have to be saved in temporary registers</div><div>the temporary registers assume the role of the permanent registers and store the result of the instruction</div><div>the commitment unit guarantees in-order commitment using a reorder buffer (queue)</div><div>when an instruction reaches the head of the queue, the data is transferred from a temporary register to a permanent register</div><div><br/></div></body></html>