lectures.alex.balgavy.eu

Lecture notes from university.
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      1 +++
      2 title = 'Memory types'
      3 +++
      4 # Memory types
      5 ## Static memories (SRAM)
      6 circuits that can retain state as long as power is applied
      7 
      8 fast, but cells require several transistors
      9 
     10 one cell has two inverters that are cross-connected — a latch
     11 
     12 ![screenshot.png](screenshot-48.png)
     13 
     14 Read operation
     15 
     16 - word line is activated, closes switches T1 and T2.
     17 - If cell in state 1, signal on b is high and signal on line b’ is low. Vice versa.
     18 
     19 Write operation
     20 
     21 - sense/write circuit drives bit lines b and b’
     22 - places appropriate value on line b and its complement on b’, activates word line
     23 - forces cell into corresponding state, retains when word line is deactivated
     24 
     25 ## Dynamic memories (DRAM)
     26 do not retain state for a long period unless accessed frequently
     27 
     28 info is stored in form of charge on a capacitor (only for tens of milliseconds)
     29 
     30 contents are periodically refreshed when they are accessed/written to
     31 
     32 example of single transistor-capacitor DRAM cell:
     33 
     34 ![screenshot.png](screenshot-49.png)
     35 
     36 A full 32M x 8 chip:
     37 
     38 ![screenshot.png](screenshot-50.png)
     39 
     40 Refresh (and read) operation:
     41 - transistor in selected cell is turned on
     42 - sense amplifier on bit line checks if charge in capacitor is above threshold value
     43 - if above, sense amplifier drives bit line to full voltage (1)
     44 - otherwise, pulls bit line to ground level
     45 
     46 Fast page mode:
     47 - each sense amplifier is also used as latch
     48 - so when a row address is applied, contents of all cells in the row are loaded into latches
     49 - so all bytes in the row can be transferred sequentially, increasing block transfer speed.
     50 
     51 ## Synchronous DRAMs
     52 operation is synced with a clock signal
     53 
     54 built-in refresh circuitry with a refresh counter to refresh specific rows
     55 
     56 ## Double-Data-Rate SDRAM
     57 
     58 large number of bits are accessed at the same time when a row address is applied
     59 
     60 data are transferred both on rising and falling edges of clock
     61 
     62 ## Rambus Memory
     63 proprietary
     64 
     65 uses fewer wires with a higher clock speed
     66 
     67 makes use of differential-signaling technique to transfer data
     68 
     69 signals are transmitted using small voltage swings of ±0.1V around reference value