Memory types.html (3565B)
1 <?xml version="1.0" encoding="UTF-8"?> 2 <!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> 3 <html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="-0.4092537462711334"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-12-17 5:28:58 PM +0000"/><meta name="latitude" content="52.37363590268605"/><meta name="longitude" content="4.836361791607864"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-12-17 6:24:57 PM +0000"/><title>Memory types</title></head><body><div><b>Static memories (SRAM)</b></div><div>circuits that can retain state as long as power is applied</div><div>fast, but cells require several transistors</div><div>one cell has two inverters that are cross-connected — a latch</div><div><img src="Memory%20types.resources/screenshot_2.png" height="411" width="557"/></div><div><br/></div><div>Read operation</div><div><ul><li>word line is activated, closes switches T1 and T2. <br/></li><li>If cell in state 1, signal on b is high and signal on line b’ is low. Vice versa.<br/></li></ul></div><div><br/></div><div>Write operation</div><div><ul><li>sense/write circuit drives bit lines b and b’<br/></li><li>places appropriate value on line b and its complement on b’, activates word line<br/></li><li>forces cell into corresponding state, retains when word line is deactivated<br/></li></ul></div><div><br/></div><div><b>Dynamic memories (DRAM)</b></div><div>do not retain state for a long period unless accessed frequently</div><div>info is stored in form of charge on a capacitor (only for tens of milliseconds)</div><div>contents are periodically refreshed when they are accessed/written to</div><div><br/></div><div>example of single transistor-capacitor DRAM cell:</div><div><img src="Memory%20types.resources/screenshot.png" height="295" width="413"/></div><div><br/></div><div>A full 32M x 8 chip:</div><div><img src="Memory%20types.resources/screenshot_1.png" height="470" width="700"/></div><div>Refresh (and read) operation:</div><div><ul><li>transistor in selected cell is turned on</li><li>sense amplifier on bit line checks if charge in capacitor is above threshold value</li><li>if above, sense amplifier drives bit line to full voltage (1)</li><li>otherwise, pulls bit line to ground level</li></ul><div><br/></div></div><div>Fast page mode:</div><div><ul><li>each sense amplifier is also used as latch</li><li>so when a row address is applied, contents of all cells in the row are loaded into latches</li><li>so all bytes in the row can be transferred sequentially, increasing block transfer speed.<br/></li></ul></div><div><br/></div><div><b>Synchronous DRAMs</b></div><div>operation is synced with a clock signal</div><div>built-in refresh circuitry with a refresh counter to refresh specific rows</div><div><br/></div><div><b>Double-Data-Rate SDRAM</b></div><div>large number of bits are accessed at the same time when a row address is applied</div><div>data are transferred both on rising and falling edges of clock</div><div><br/></div><div><b>Rambus Memory</b></div><div>proprietary</div><div>uses fewer wires with a higher clock speed</div><div>makes use of differential-signaling technique to transfer data</div><div>signals are transmitted using small voltage swings of ±0.1V around reference value</div></body></html>