Memory operations & instructions.md (2066B)
1 +++ 2 title = 'Memory operations & instructions' 3 +++ 4 # Memory operations & instructions 5 ## Memory operations 6 7 to execute an instruction, processor control circuits have to cause word/words containing instruction to be transferred from memory to processor (with operands and results) 8 9 basic operations 10 11 - read — transfers copy of contents of memory location to processor 12 - write — transfers item of info from processor to a memory location 13 14 ## RISC vs CISC instruction sets 15 (most processors have a compromise) 16 17 RISC (Reduced Instruction Set Computers) 18 19 - simple addressing modes 20 - each instruction fits in one word 21 - fewer instructions in set 22 - arithmetic/logic only on operands in processor registers 23 - load/store architecture: no direct transfer between memory locations, must be through processor register 24 - programs tend to be larger in size (more, simpler instructions) 25 26 CISC (Complex Instruction Set Computers) 27 28 - more complex addressing modes, e.g.: 29 - autoincrement— access operand through effective address in passed register, then increment contents of said register 30 - autodecrement — contents of passed register are decremented and then used as effective address of operand 31 - relative — effective address is determined using index mode with PC instead of register 32 - instructions don’t have to fit into a single word 33 - more complex instructions 34 - arithmetic/logic also on both memory locations and registers 35 - not constrained to load/store architecture 36 37 ## Instruction Execution 38 39 the processor has a program counter (PC) register, holds address of next instruction 40 41 processor circuits use info in PC to fetch and execute instructions in order of increasing address (straight-line sequencing) 42 43 executing an instruction 44 45 1. Instruction fetch — instruction fetched from mem location stored in PC and put in instruction register 46 47 2. Instruction execute — instruction is examined and the operation is performed, PC is incremented by 4. 48 49 branch instructions load new address into PC, allow conditional jumping (jump if greater/less than)