index.md (669B)
1 +++ 2 title = 'Memory delays' 3 +++ 4 # Memory delays 5 another cause of pipeline stalls is a delay from memory access 6 7 for example, because of a cache miss 8 9 instructions: 10 - Load R2, (R3) 11 - Subtract R9, R2, #30 12 13 even if data for load is found in cache, operand forwarding can’t be done the same way — data read from cache are not available until they are in RY at start of cycle 5 14 15 subtract must be stalled for one cycle to delay ALU operation 16 17  18 19 eliminating the one-cycle stall: 20 21 - compiler inserts a useful instruction between load and memory-dependent instruction 22 - otherwise, hardware stalls automatically (or compiler inserts NOP)