index.md (1612B)
1 +++ 2 title = 'Data path & instructions' 3 +++ 4 # Data path & instructions 5 ## Overall data path: 6 organised in five stages, according to steps executed 7 1. Instruction fetch 8 2. Load from source registers 9 3. ALU computes 10 4. Memory access 11 5. Save to destination register 12 13  14 15 ## Instruction fetch section 16 address for memory access come from PC for instructions, from RZ for operands 17 instruction address generator (includes PC) updates contents of PC after fetch 18 instruction loaded into IR, examined by control circuitry to generate signals 19 immediate values are sign-extended to 32 bits 20 21  22 23 ## Instruction fetch & execution in steps 24 with an example instruction: ADD R3, R4, R5 25 26 1. Fetch instruction and place in IR 27 2. Contents of R4, R5 move to RA, RB 28 3. Control circuitry sets MuxB to input 0 (RB), causes ALU to add RA+RB into RZ 29 30 4. MuxY selects input 0, RZ moves to RY. Control circuitry connects destination address to input for port C of register file 31 32 5. Write RY to R3 33 34 ## Waiting for memory 35 36 when requested info isn’t in cache and has to be fetched from main memory, multiple clock cycles may be needed 37 38 processor-memory interface circuit generates a Memory Function Completed (MFC) signal 39 40 if the data is in cache, MFC signal is asserted before the end of the clock cycle 41 42 ## How are control signals generated? 43 either hardwired or microprogrammed control 44 45 hardwired — setting of signals depends on: 46 47 - contents of step counter 48 - contents of instruction register 49 - results of computation/comparison 50 - external input signals (e.g. interrupts)