Data path & instructions.html (3107B)
1 <?xml version="1.0" encoding="UTF-8"?> 2 <!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> 3 <html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="-0.3448867201805115"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-12-16 10:38:45 PM +0000"/><meta name="latitude" content="52.37359297352734"/><meta name="longitude" content="4.836362365770766"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-12-16 10:39:19 PM +0000"/><title>Data path & instructions</title></head><body><div><span style="font-weight: bold;">Overall data path:</span></div><div>organised in five stages, according to steps executed</div><ol><li>Instruction fetch</li><li>Load from source registers</li><li>ALU computes</li><li>Memory access</li><li>Save to destination register</li></ol><div><br style="font-weight: bold;"/></div><div><img src="Data%20path%20&%20instructions.resources/screenshot_1.png" height="983" width="666"/><br/></div><div><br/></div><div><span style="font-weight: bold;">Instruction fetch section</span></div><div>address for memory access come from PC for instructions, from RZ for operands</div><div>instruction address generator (includes PC) updates contents of PC after fetch</div><div>instruction loaded into IR, examined by control circuitry to generate signals</div><div>immediate values are sign-extended to 32 bits</div><div><br/></div><div><img src="Data%20path%20&%20instructions.resources/screenshot.png" height="469" width="596"/></div><div><br/></div><div><span style="font-weight: bold;">Instruction fetch & execution in steps</span></div><div>with an example instruction: ADD R3, R4, R5</div><div><br/></div><ol><li>Fetch instruction and place in IR</li><li>Contents of R4, R5 move to RA, RB</li><li>Control circuitry sets MuxB to input 0 (RB), causes ALU to add RA+RB into RZ</li><li>MuxY selects input 0, RZ moves to RY. Control circuitry connects destination address to input for port C of register file</li><li>Write RY to R3</li></ol><div><br/></div><div><span style="font-weight: bold;">Waiting for memory</span></div><div>when requested info isn’t in cache and has to be fetched from main memory, multiple clock cycles may be needed</div><div>processor-memory interface circuit generates a Memory Function Completed (MFC) signal</div><div>if the data is in cache, MFC signal is asserted before the end of the clock cycle</div><div><br/></div><div><span style="font-weight: bold;">How are control signals generated?</span></div><div>either hardwired or microprogrammed control</div><div><br/></div><div>hardwired — setting of signals depends on:</div><ul><li>contents of step counter</li><li>contents of instruction register</li><li>results of computation/comparison</li><li>external input signals (e.g. interrupts)</li></ul><div><br/></div><div><br/></div></body></html>