Basic processing unit.md (1934B)
1 +++ 2 title = 'Basic processing unit' 3 +++ 4 # Basic processing unit 5 ## Organisation and basic processing cycle 6 Execution of complete instruction: 7 1. Fetch instruction 8 9 - fetch instruction pointed to by PC, put it into IR (instruction register) 10 - increment PC by number of bytes 11 - decode IR and execute instruction specified in IR 12 13 2. Fetch operand 14 3. Perform operation 15 16 - use memory operand / NOP 17 18 4. Store result 19 20 Components: 21 22 - CPU bus in the middle — means of communication between different components 23 - connects every pair of components 24 - bus width is based on the size of the word (bits), e.g. 32 or 64 depending on the ISA 25 - bus can only transport that many bits max 26 - every component can read at the same time 27 - only one component can write at a certain time 28 - PC (program counter) — counts instructions, notes which is next 29 - Processor-memory interface — registers 30 - Y register — internal, cannot be accessed 31 - MAR (memory address register) — stores location of various data in memory 32 - MDR (memory data register) — stores values (data) to be stored 33 - IR (instruction register) — stores the next instruction 34 - Decoder — changes (decodes) an instruction into signals 35 - Register file (R0, R1, R2,…) 36 - package multiple registers together 37 - add single gates for input and output -> lower energy requirements 38 - but with this, only one register can read/write the bus at a time. 39 - so add another bus `¯\_(ツ)_/¯` energy requirement is the limit 40 - ALU — computes stuff 41 42 Register gating: 43 44 - controls who can access the bus 45 - Put gates before each component to control input/output 46 47 Register transfer (e.g. R1 to R3 — all happens at once): 48 1. Addr_out = R1 49 2. R_out 50 3. Addr_in=R3 51 4. R_in 52 53 Load from memory: 54 1. Ri_out, MAR_in, read 55 2. MDR_inE, WMFC 56 3. MDR_out, Ri_in 57 58 Store to memory: 59 1. Ri_out, MAR_in 60 2. Rj_out, MDR_in, write 61 3. MDR_outE, WMFC