index.md (2386B)
1 +++ 2 title = 'Principles of IO hardware' 3 +++ 4 # Principles of IO hardware 5 IO devices available to software via an interface 6 7 - character devices: all IO occurs as stream of bytes 8 - block devices: all IO occurs in units of randomly accessible blocks 9 10 device controller 11 12 - located between actual device and computer 13 - offers electronic interface via IO registers 14 - R/W those registers to ask controller to perform actions 15 16 example: parallel port 17 18  19 20 accessing IO registers 21 22 - port-mapped IO (PMIO): 23 - IO registers are accessed via dedicated port numbers and special instructions 24 - e.g. inb instruction 25 - memory-mapped IO (MMIO): 26 - IO registers are mapped into address of main memory 27 - can be accessed with a simple mov 28 - intel x86 is hybrid, does both PMIO and MMIO 29 30 IO ports have a specification from the manufacturer (e.g. IBM PC) 31 32 waiting for requests: 33 34 - we can send commands to devices, but what if requested operation takes time? 35 - polling: 36 - most devices offer status bits in registers to signal that request has been finished (incl. error code) 37 - OS can poll this status bit ("*polling*") 38 - is this a good solution? not a general purpose solution, but good if we know it'll complete in a short amount of time. 39 - interrupts: 40 - device controller can trigger interrupts to signal that IO requesst is complete 41 - for device, means changing voltage on an electrical line 42 - each controller has interrupt vector assigned 43 - CPU runs vector-specific handler when interrupt occurs 44 - process one interrupt at a time 45 46 data exchange between device and CPU 47 48 - how do we transfer data from hard disk to memory? 49 - program disk controller to read sector 50 - wait for interrupt 51 - read a device register sizeof(sector) consecutive times 52 - repeat for next sector 53 - problem? yes sir. CPU cycles can be spent in a better way 54 - so just let hardware do the copying -- Direct Memory Access! 55 - on ISA systems, there was a dedicated DMA controller (third-party) 56 - on PCI (and PCIe) systems each PCI device can become "Bus Master" and perform DMA (first-party DMA) 57 - device and DMA controller are combined 58 - you have to trust your hardware (or use an IO MMU) 59 - embedded systems still have dedicated DMA controller 60 - disk controller still uses own buffers